PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 210

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
REGISTER 17-8:
DS39616B-page 208
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
-n = Value at POR
BRFEN: Breakpoint Fault Enable bit
1 = Enable fault condition on a breakpoint (i.e., only when HDMIN = 1)
0 = Disable fault condition
FLTBS: Fault B Status bit
1 = FLTB is asserted;
0 = No Fault
FLTBMOD: Fault B Mode bit
1 = Cycle-by-cycle mode: Pins are inactive for the remainder of the current PWM period, or until
0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTB is deasserted and
FLTBEN: Fault B Enable bit
1 = Enable Fault B
0 = Disable Fault B
FLTCON: Fault Configuration bit
1 = FLTA , FLTB or both deactivates all PWM outputs
0 = FLTA or FLTB deactivates PWM[5:0]
FLTAS: Fault A Status bit
1 = FLTA is asserted;
0 = No Fault
FLTAMOD: Fault A Mode bit
1 = Cycle-by-cycle mode: Pins are inactive for the remainder of the current PWM period, or until
0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTA is deasserted and
FLTAEN: Fault A Enable bit
1 = Enable Fault A
0 = Disable Fault A
bit 7
BRFEN
FLTCONFIG: FAULT CONFIGURATION REGISTER
R/W-0
Note 1: Unimplemented in PIC18F2X31 devices; maintain these bits clear.
if FLTBMOD = 0, cleared by the user
if FLTBMOD = 1, cleared automatically at beginning of the new period when FLTB is
deasserted
FLTB is deasserted. FLTBS is cleared automatically when FLTB is inactive (no fault present).
FLTBS is cleared by the user only.
If FLTAMOD = 0, cleared by the user
If FLTAMOD = 1, cleared automatically at beginning of the new period when FLTA is
deasserted.
FLTA is deasserted. FLTAS is cleared automatically.
FLTAS is cleared by the user only.
FLTBS
R/W-0
(1)
FLTBMOD
(1)
R/W-0
(1)
(1)
W = Writable bit
‘1’ = bit is set
Preliminary
(1)
FLTBEN
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared
FLTCON
R/W-0
FLTAS
R/W-0
 2003 Microchip Technology Inc.
FLTAMOD
x = bit is unknown
R/W-0
FLTAEN
R/W-0
bit 0