PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 138

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
14.4.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary PWM
output signal is output on the P1B pin (Figure 14-4). This
mode can be used for half-bridge applications, as shown
in Figure 14-5, or for full-bridge applications where four
power switches are being modulated with two PWM
signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC6:PDC0, sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 14.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 14-5:
DS39682B-page 136
HALF-BRIDGE MODE
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
PIC18F4X5J10
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
P1A
P1B
PIC18F4XJ10
P1A
P1B
FET
Driver
FET
Driver
Preliminary
FET
Driver
FET
Driver
FIGURE 14-4:
Note 1: At this time, the TMR2 register is equal to the
P1A
P1B
td = Dead-Band Delay
Load
V+
V-
(2)
(2)
V+
V-
2: Output signals are shown as active-high.
(1)
PR2 register.
Duty Cycle
td
Load
Period
td
HALF-BRIDGE PWM
OUTPUT
© 2006 Microchip Technology Inc.
FET
Driver
FET
Driver
+
V
-
+
V
-
(1)
Period
(1)