PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 174

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
15.4.7
In I
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 15-17). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
‘0’ and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
FIGURE 15-17:
TABLE 15-3:
DS39682B-page 172
Note 1:
CY
2
C Master mode, the Baud Rate Generator (BRG)
) on the Q2 and Q4 clocks. In I
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
F
CY
2
C™ interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE w/BRG
SSPM3:SSPM0
BAUD RATE GENERATOR BLOCK DIAGRAM
SCLx
2
C Master mode, the
SSPM3:SSPM0
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
* 2
Reload
Control
Preliminary
CLKO
Reload
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
15.4.7.1
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be pos-
sible to change one or both baud rates back to a
previous value by changing the BRG reload value.
BRG Down Counter
2
SSPxADD<6:0>
C specification (which applies to rates greater than
BRG Value
0Ch
18h
1Fh
63h
09h
27h
02h
09h
00h
Baud Rate and Module
Interdependence
© 2006 Microchip Technology Inc.
F
OSC
(2 Rollovers of BRG)
/4
2
C Master mode at
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)