PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 151

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.3.3
To enable the serial port, MSSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPxCON registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
• SDIx is automatically controlled by the SPI module
• SDOx must have TRISC<5> (or TRISD<2>) bit
• SCKx (Master mode) must have TRISC<3> (or
• SCKx (Slave mode) must have TRISC<3> (or
• SSx must have TRISA<5> (or TRISD<3>) bit set
FIGURE 15-2:
© 2006 Microchip Technology Inc.
cleared
TRISD<0>) bit cleared
TRISD<0>) bit set
SPI™ Master SSPM3:SSPM0 = 00xxb
ENABLING SPI I/O
MSb
PROCESSOR 1
Serial Input Buffer
SPI™ MASTER/SLAVE CONNECTION
Shift Register
(SSPxBUF)
(SSPxSR)
LSb
SDOx
SCKx
SDIx
Preliminary
Serial Clock
PIC18F45J10 FAMILY
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
15.3.4
Figure 15-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
SDOx
SCKx
SDIx
SPI™ Slave SSPM3:SSPM0 = 010xb
TYPICAL CONNECTION
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SSPxBUF)
(SSPxSR)
LSb
DS39682B-page 149