PIC18F2510-I/ML Microchip Technology Inc., PIC18F2510-I/ML Datasheet - Page 181

• Manufacturer Part Number: PIC18F2510-I/ML
• Description: Microcontroller; 32 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2510-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(T
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for T
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode
(Figure 15-23).
15.4.12.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-23:
FIGURE 15-24:
© 2006 Microchip Technology Inc.
BRG
) and the SCLx pin is deasserted (pulled high).
ACKNOWLEDGE SEQUENCE
TIMING
SCLx
SDAx
WCOL Status Flag
Note: T
Note: T
Sequence
Write to SSPxCON2,
Falling edge of
9th clock
SSPxIF
SDAx
SCLx
BRG
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
Acknowledge sequence starts here,
ACK
= one Baud Rate Generator period.
= one Baud Rate Generator period.
set PEN
SSPxIF set at
the end of receive
Enable
ACKEN = 1, ACKDT = 0
write to SSPxCON2
BRG
T
T
BRG
BRG
. The SCLx pin
SDAx asserted low before rising edge of clock
to set up Stop condition
bit,
D0
8
ACKEN
T
SCLx brought high after T
BRG
Preliminary
Cleared in
software
P
T
SCLx = 1 for T
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
BRG
T
BRG
PIC18F45J10 FAMILY
ACK
15.4.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDAx line low. When the SDAx
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A T
cleared and the SSPxIF bit is set (Figure 15-24).
15.4.13.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
PEN bit (SSPxCON2<2>) is cleared by
T
hardware and the SSPxIF bit is set
BRG
BRG
BRG
9
SSPxIF set at the end
of Acknowledge sequence
, followed by SDAx = 1 for T
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
(Baud Rate Generator rollover count)
Cleared in
software
BRG
BRG
later, the PEN bit is
DS39682B-page 179