PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 29

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY
To enable the filter of equalizer inside the VIP, set bit TICCMR:FIL to ’1’ (please refer to
VIP channel config description in DELIC-LC/-PB SW User’s Manual). The adaptive
amplifier control of the equalizer should be set to automatic. Set bit TICCMR:AAC (1:0)
to ’00’ (please refer to VIP channel config description in DELIC-LC/-PB SW User’s
Manual).
3.2.3
The receive PLL (RxPLL) recovers bit timing from a comparator output signal.
Note: The recommended setting for the receive PLL is integral behaviour. This is
Comparator threshold.
The comparator has a threshold of 80 % with respect to the signal stored by the peak
detector.
Phase adjustment.
The RxPLL performs tracking after detecting phase shifts of the same polarity in four
consecutive pulses. A phase adjustment is done by adding or subtracting 65 ns or
32.5 ns (one U
(default TICCMR:PLLS ’0’), to or from the 384 kHz receive data clock.
3.2.4
In order to further reduce the bit error rate in severe conditions, the VIP performs
oversampling of the received signal and uses majority decision logic. The process of
receive signal oversampling is illustrated in
• Each received bit is sampled 6 times at 15.36-MHz clock intervals inside the estimated
• The samples obtained are compared to a threshold of 50 % with respect to the signal
Note: The recommended setting for signal oversampling is TICCMR:OWIN =’011’.
Data Sheet
bit window.
stored by the peak detector.
If at least ’n’ samples have an amplitude exceeding the 50 % threshold, a logical ’1’ is
detected; otherwise a logical ’0’ (no signal) is assumed.
The parameter ’n’ is programmed in steps of 2 in bits OWIN(2:0) of IOM-2000 CMD
register.
enabled by setting bit TICCMR:PLLINT=’1’ (please refer to VIP channel
config description in DELIC-LC/-PB SW User’s Manual).
For detailed description please refer to DELIC-LC/-PB Data Sheet.
Receive PLL
Receive Signal Oversampling
PN
oscillator period), programmable by the DELIC command bit ’PLLS’
21
Figure
13:
Interface Description
PEB 20590
PEB 20591
2001-03-01