PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 37

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY
3.3.5
The receive signal is oversampled within the receive clock period, and a majority logic is
used to reduce the bit error rate in severe conditions.
• As illustrated in Figure 19, each received bit is sampled 29 times at 7.68-MHz clock
• The samples obtained are compared against a threshold of 35% with respect to the
Figure 19
3.3.6
A buffer in the VIP is designed as a wander-tolerant system, required in LT-T and LT-S
modes. In LT-T mode, the VIP is clock slave to the CO, and the data clocks of the S/T
interface and the IOM-2000 interface have a time dependent phase relationship. The
buffer compensates a maximum phase wander of ± 20 s.
A slip detector indicates when this limit is exceeded. The ’SLIP’ bit in VIP Status Register
issues a warning to the DELIC when a slip of 20 s in either direction was detected. The
VIP buffers are reset to their default positions automatically.
Note: In case of frame slip, the phase relationship between the IOM-2000 interface and
Data Sheet
intervals inside the estimated bit window.
signal stored by the peak detector.
If at least a number of ’n’ samples have an amplitude exceeding the threshold, a
logical ’0’ is detected; otherwise a logical ’1’ (no signal) is assumed. The parameter ’n’
is programmed by the OWIN command bits.
the S/T interface is arbitrary. A re-alignment of the wander buffer after a slip may
result in loss of data.
Receive Signal Oversampling
Elastic Buffer
Receive Signal Oversampling in S/T Receiver
29
Interface Description
PEB 20590
PEB 20591
2001-03-01