PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 33

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY
3.3.2
Receiver Characteristics
The receiver input stages consist of a differential amplifier, followed by a peak detector
and a set of comparators. Additional noise immunity is achieved by digital oversampling
after the comparators, meaning that the sampling of the received bit is controlled digitally
and dependent on the mode (Command Register).
The peak detector requires at most 2 s to reach the peak value while storing the peak
level for at least 250 s. The data detection thresholds are set to 35 % of the peak
voltage to increase the performance in extended passive bus configurations. However,
they are never lower than 85 mV with respect to the line signal level in order to increase
noise immunity.
The level detector monitors the line input signals to detect whether an INFO signal is
present. It is possible to indicate an incoming signal during activated analog loop.
Figure 16
3.3.3
The VIP generates the internal clocks with a PLL, that receives a 15.36-MHz signal via
an on-chip oscillator either from an external crystal or from the DELIC.
•
VIP Operating Mode
LT-S or U
LT-T mode
Data Sheet
PN
S/T Transceiver
Receive Clock Recovery
mode
Receiver Functional Blocks
All Clocks Synchronized to
IOM-2000 interface data clock provided by the DELIC on
DCL_2000 pin
Data clock provided by the Central Office
1.65 V
25
Interface Description
PEB 20590
PEB 20591
2001-03-01