PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 36

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PRELIMINARY
Data Sheet
Jitter Requirements
In LT-T mode, ITU-T I.430 specifies a maximum jitter in transmit direction of – 7 % to
+ 7 %, resulting in 730 ns peak-to-peak.
This specification will be met by the VIP provided that the master clock source is
accurate within 100 ppm.
3.3.4
In LT-T configurations, the DELIC receives the CO reference clock via the XCLK input
pin, which is connected to VIP’s REFCLK output.
The VIP reference clock channel is programmed by the DELIC. The source may be
either one of the 8 VIP channels operated in LT-T mode or VIP’s INCLK pin, when
several VIP’s are connected to the IOM-2000 interface (see
•
Figure 18
Reference Clock
Trunk (LT-T)
Ch_0
CH_7
Ch_0
Ch_0
Ch_7
Ch_7
Reference Clock Selection in LT-T Mode
LT-T Reference Clock Channel Selection for Cascaded VIPs
VIP_0
VIP_1
VIP_2
INCLK
INCLK
REFCLK
REFCLK
28
DR
Ch_0
Ch_7
XCLK
VIP_n
REFSEL
Figure
DELIC
INCLK
Interface Description
EXREF
18).
PEB 20590
PEB 20591
2001-03-01
REFCLK