PEB20591HV22XP Lantiq, PEB20591HV22XP Datasheet - Page 7

• Manufacturer Part Number: PEB20591HV22XP
• Manufacturer: Lantiq

Specifications of PEB20591HV22XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

List of Figures
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Data Sheet
Logic Symbol PEB 20591 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VIP in Mixed S/T and U
VIP in a Small PBX Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DELIC-PB and VIP in a PC Card for 8/16 S/T Interfaces . . . . . . . . . . . 8
AMI Coding on the U
Receive Signal Oversampling on U
S/T Interface Line Code (without Code Violation) . . . . . . . . . . . . . . . . 24
LT-T Reference Clock Channel Selection for Cascaded VIPs. . . . . . . 28
Receive Signal Oversampling in S/T Receiver . . . . . . . . . . . . . . . . . . 29
Overview of IOM-2000 Interface Structure (Example with One VIP) . . 30
IOM-2000 Data Sequence (1 VIP with 8 Channels) . . . . . . . . . . . . . . 32
IOM-2000 Data Order (3 VIPs with 24 Channels) . . . . . . . . . . . . . . . . 33
IOM-2000 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External Transceiver Circuitry of the VIP in U
Wiring Configurations in User Premises (LT-S Mode) . . . . . . . . . . . . . 49
Internal and External Loop-Back Modes . . . . . . . . . . . . . . . . . . . . . . . 50
Top-Level Block Diagram of the VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Symbol PEB 20590 (72 of 80 Pins used) . . . . . . . . . . . . . . . . . . . 6
Pin Diagram, PEB 20590 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Diagram, PEB 20591 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
U
Transceiver Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Equalizer Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Frame Structure at Reference Points S and T (ITU-T I.430) . . . . . . . . 23
Receiver Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Recovery in LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Recommended Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Input/Output Wave Form for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 42
JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1:1 Transformer Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Overview of External Circuitry of the VIP in S/T Mode . . . . . . . . . . . . 47
External S/T Transmitter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External S/T Receiver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PN
Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PN
PN
Interface in VIP . . . . . . . . . . . . . . . . . . . . . . . 19
Line Cards (e.g. 8 S/T and 16 U
PN
Interface . . . . . . . . . . . . . . . . . 22
PN
Mode . . . . . . . . . . . . 47
PN
PEB 20590
PEB 20591
). . . . . . . 7
2001-03-01
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