MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 163

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
Note:
4.28.2.10
154.
155.
4.28.2.11
Note:
4.28.3
4.28.3.1
4.28.3.1.1
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When reading this address, the
buffered and synchronized state of the pin is returned if the associated data direction register bit is set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This is independent of any
other configuration
4.28.3.1.2
This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the
data direction register is ignored
4.28.3.1.3
This is a read-only register and always returns the buffered and synchronized state of the pin
Freescale Semiconductor
156.
Address 0x0122-0x017F
Address 0x0121
Reset
i
W
W
R
R
Field
PTIE
1–0
(155)
Read: Anytime.
u = Unaffected by reset
Read: Anytime.
Write: Unimplemented. Writing to this register has no effect.
Write: Unimplemented. Writing to this register has no effect.
Port E input data— A read always returns the buffered input state of the associated pin.It can be used to detect overload or short
circuit conditions on output pins.
Functional Description
Port E Input Register (PTIE)
PIM Reserved Registers
Registers
7
0
0
7
0
u
Data register (PORTx)
Data direction register (DDRx)
Input register (PTIx)
(Figure
46).
6
0
0
6
0
u
(Figure
Table 241. PTIE Register Field Descriptions
46).
Table 240. Port E Input Register (PTIE)
MM912_634 Advance Information, Rev. 4.0
Table 242. PIM Reserved Register
5
0
0
5
0
u
4
0
0
4
0
u
Description
3
0
0
3
0
u
Port Integration Module (S12IPIMV1)
2
0
0
2
0
u
(Figure
46).
PTIE1
1
0
0
1
u
Access: User read
Access: User read
PTIE0
0
0
0
0
u
(156)
(154)
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