MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 216

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Access direction can also be used to qualify a match for Comparator B in the same way as described for Comparator C in
Table
4.32.4.2.1.3
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
Table
DBGADH. Access direction can also be used to qualify a match for Comparator A in the same way as described for Comparator
C in
4.32.4.2.1.4
Comparator A features an NDB control bit, which allows data bus comparators to be configured to either trigger on equivalence
or trigger on difference. This allows monitoring of a difference in the contents of an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the
corresponding mask bit (DBGADHM/DBGADLM) so that it is ignored in the comparison. A match occurs when all data bus bits
with corresponding mask bits set are equivalent. If all mask register bits are clear, then a match is based on the address bus only,
the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any data bus bit with
corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored and prevents a match because no
difference can be detected. In this case address bus equivalence does not cause a match.
Freescale Semiconductor
Note:
179.
SZE
0
0
0
0
0
0
1
1
1
1
1
1
Table
319.
lists access considerations with data bus comparison. On word accesses the data byte of the lower address is mapped to
Word and byte accesses of ADDR[n]
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain
the exact address from the code.
Word accesses of ADDR[n] only
SZ
X
X
X
X
X
X
0
0
0
0
1
1
319.
Condition For Valid Match
DBGADHM,
DBGADLM
Comparator A
Comparator A Data Bus Comparison NDB Dependency
$FFFF
$FFFF
$FFFF
$FF00
$00FF
$00FF
$00FF
$FF00
$FF00
$0000
$0000
$0000
Byte
Word
Byte, data(ADDR[n])=DH
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Word
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte
Byte, data(ADDR[n])=DH
Table 321. Comparator A Matches When Accessing ADDR[n]
Table 320. Comparator B Access Size Considerations
Access DH=DBGADH, DL=DBGADL
MM912_634 Advance Information, Rev. 4.0
Comp B Address
ADDR[n]
ADDR[n]
(179)
RWE
0
0
SZE
0
1
No data bus comparison
Match data(ADDR[n])
Match data(ADDR[n+1])
Possible unintended match
Match data(ADDR[n], ADDR[n+1])
Possible unintended match
No data bus comparison
Match only data at ADDR[n+1]
Match only data at ADDR[n]
Match data at ADDR[n] & ADDR[n+1]
No data bus comparison
Match data at ADDR[n]
SZ8
X
0
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
MOVB #$BYTE ADDR[n]
Comment
LDD ADDR[n]
Examples
216