MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 208

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The priorities described in
followed by the match on the lower channel number (0,1,2).
4.32.3.2.7.4
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly to a channel. Should a
match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the
module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These
flags cannot be cleared by software, they are cleared only when arming the module. A set flag does not inhibit the setting of other
flags. Once a flag is set, further comparator matches on the same channel in the same session have no affect on that flag.
4.32.3.2.8
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module register address map.
Comparator A consists of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask
registers and a control register). Comparator B consists of four register bytes (three address bus compare registers and a control
register). Comparator C consists of four register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g.
Comparator B data bus and data bus masking) read as zero and cannot be written. The control register for comparator B differs
from those of comparators A and C.
Freescale Semiconductor
Address: 0x0027
Reset
SC[3:0]
0100
0101
1000
1001
1010
0110
0111
1011
1100
1101
1110
0x002A
1111
W
0x0028
0x0029
R
7
0
0
Debug Match Flag Register (DBGMFR)
Comparator Register Descriptions
Table 323
ADDRESS MEDIUM
ADDRESS HIGH
6
0
0
= Unimplemented or Reserved
CONTROL
Table 296. State3 — Sequencer Next State Selection
dictate that in the case of simultaneous matches, a match leading to final state has priority
Table 297. Debug Match Flag Register (DBGMFR)
Table 298. Comparator Register Layout
Either Match1 or Match2 to State1....... Match0 to Final State
Either Match1 or Match2 to Final State....... Match0 to State1
MM912_634 Advance Information, Rev. 4.0
Description (Unspecified matches have no effect)
5
0
0
Match2 to State2........ Match0 to Final State
Match0 to State2....... Match2 to Final State
Match1 to Final State
Match0 to Final State
4
0
0
Match1 to State2
Reserved
Reserved
Reserved
Reserved
Reserved
Read/Write
Read/Write
Read/Write
3
0
0
MC2
2
0
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
MC1
1
0
MC0
0
0
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