MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 193

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is
initiated by the target MCU by issuing a negative edge on the BKGD pin. The hardware handshake protocol in
the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an
electrical conflict on the BKGD pin.
The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse,
the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters stop
while the host issues a hardware command (e.g., WRITE_BYTE), the target discards the incoming command due to the stop
being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued
in this case. After a certain time the host (not aware of stop) should decide to abort any possible pending ACK pulse in order to
be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its
corresponding ACK, can be aborted.
4.31.4.8
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding
ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles
and then driving it high for one serial clock cycle, providing a speedup pulse.By detecting this long low pulse in the BKGD pin,
the target executes the SYNC protocol, see
pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been
completed the host is free to issue new BDM commands. For BDM firmware READ or WRITE commands it can not be
guaranteed that the pending command is aborted when issuing a SYNC before the corresponding ACK pulse. There is a short
latency time from the time the READ or WRITE access begins until it is finished and the corresponding ACK pulse is issued. The
latency time depends on the firmware READ or WRITE command that is issued and on the selected bus clock rate. When the
SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK
pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL(171) command can not be aborted. Only the corresponding ACK
pulse can be aborted by the SYNC command.
Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter
than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative
edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD
pin low, in order to allow the negative edge to be detected by the target.In this case, the target will not execute the SYNC protocol
but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when
there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The
worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target
the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the
accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not
a read command the short abort pulse could be used. After a command is aborted the target assumes the next negative edge,
after the abort pulse, is the first bit of a new BDM command.
Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider
the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length.
Freescale Semiconductor
Hardware Handshake Abort Procedure
The only place the BKGD pin can have an electrical conflict is when one side is driving low
and the other side is issuing a speedup pulse (high). Other “highs” are pulled rather than
driven. However, at low rates the time of the speedup pulse can become lengthy and so the
potential conflict time becomes longer as well.
The ACK pulse does not provide a timeout. This means for the GO_UNTIL(171) command
that it can not be distinguished if a stop has been executed (command discarded and ACK
not issued) or if the “UNTIL” condition (BDM active) is just not reached yet. Hence in any
case where the ACK pulse of a command is not issued the possible pending command
should be aborted before issuing a new command. See the handshake abort procedure
described in
The details about the short abort pulse are being provided only as a reference for the reader
to better understand the BDM internal behavior. It is not recommended that this procedure
be used in a real application.
Section 4.31.4.8, “Hardware Handshake Abort
Section 4.31.4.9, “SYNC — Request Timed Reference
MM912_634 Advance Information, Rev. 4.0
NOTE
NOTE
NOTE
Procedure”.
Pulse”, and assumes that the
Figure 61
specifies
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