MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 334

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.41.3.8
This read-only register contains information about the ongoing D2D interface transaction. For a write transaction the data
becomes valid at the begin of the transaction. For a read transaction the data will be updated during the transaction and is
finalized when the transaction is acknowledged by the target. In error cases the user can track back what has happened.
Both D2DDATA and D2DADR can be read with byte accesses.
4.41.4
4.41.4.1
Out of reset the interface is disabled. The interface must be initialized by setting the interface clock speed, the time-out value,
the transfer width and finally enabling the interface. This should be done using a 16-bit write or if using 8-bit write D2DCTL1 must
be written before D2D2CTL0.D2DEN=1 is written. Once it is enabled in normal modes, only a reset can disable it again
(write-once feature).
4.41.4.2
A transaction on the D2D Interface is triggered by writing to either the 256 byte address window or reading from the address
window (see STAA/LDAA 0/1 in the next figure). Depending on which address window is used a blocking or a non-blocking
transaction is performed. The address for the transaction is the 8-bit wide window relative address. The data width of the CPU
read or write instructions determines if 8-bit or 16-bit wide data are transferred. There is always only one transaction active.
Figure 119
For all 16-bit read/write accesses of the CPU the addresses are assigned according the big-endian model:
addr: byte-address (8 bit wide) inside the blocking or non-blocking window, as provided by the CPU and transferred to the D2D
target word: CPU data, to be transferred from/to the D2D target The application must care for the stretched CPU cycles (limited
by the TIMOUT value, caused by blocking or consecutive accesses), which could affect time limits, including COP (computer
operates properly) supervision. The stretched CPU cycles cause the “CPU halted” phases (see
Freescale Semiconductor
Reset
DATA
Field
15:0
Offset 0x6/0x7
W
R
word [15:8]: addr
shows the various types of transactions explained in more detail below.
Transaction Data — Those read-only bits contain the data of the transaction
15
0
Functional Description
D2DI Data Buffer Register (D2DDATA)
Initialization
Transactions
14
0
13
0
12
0
Table 499. D2DI Data Buffer Register Bit Descriptions
Table 498. D2DI Data Buffer Register (D2DDATA)
word[7:0]: addr+1
11
0
MM912_634 Advance Information, Rev. 4.0
10
0
9
0
Description
DATA15:0
8
0
7
0
6
0
5
0
4
0
Figure
3
0
119).
2
0
Access: User read
1
0
0
0
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