MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 179

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.30.4
The INT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector
requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections
below.
4.30.4.1
The CPU handles both reset requests and interrupt requests. A priority decoder is used to evaluate the priority of pending
interrupt requests.
4.30.4.2
The INT module contains a priority decoder to determine the priority for all interrupt requests pending for the CPU. If more than
one interrupt request is pending, the interrupt request with the higher vector address wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
Since an interrupt vector is only supplied at the time when the CPU requests it, it is possible that a higher priority interrupt request
could override the original interrupt request that caused the CPU to request the vector. In this case, the CPU will receive the
highest priority vector and the system will process this interrupt request first, before the original interrupt request is processed.
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has
been recognized, but prior to the CPU vector request), the vector address supplied to the CPU will default to that of the spurious
interrupt vector.
4.30.4.3
The INT module supports three system reset exception request types (please refer to the Clock and Reset generator module for
details):
4.30.4.4
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon request by the CPU is
shown in
Freescale Semiconductor
1.
2.
3.
1.
2.
3.
(Vector base + 0x00F8)
(Vector base + 0x00F6)
Vector Address
The local interrupt enabled bit in the peripheral module must be set.
The I bit in the condition code register (CCR) of the CPU must be cleared.
There is no SWI, TRAP, or X bit maskable request pending.
Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable)
Clock monitor reset request
COP watchdog reset request
Table
0xFFFC
0xFFFE
0xFFFA
Functional Description
258.
S12S Exception Requests
Interrupt Prioritization
Reset Exception Requests
Exception Priority
All non I bit maskable interrupt requests always have higher priority than the I bit maskable
interrupt requests. If the X bit in the CCR is cleared, it is possible to interrupt an I bit
maskable interrupt by an X bit maskable interrupt. It is possible to nest non maskable
interrupt requests, e.g., by nesting SWI or TRAP calls.
Care must be taken to ensure that all interrupt requests remain active until the system
begins execution of the applicable service routine; otherwise, the exception request may not
get processed at all or the result may be a spurious interrupt request (vector at address
(vector base + 0x0080)).
(161)
Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable)
Clock monitor reset
COP watchdog reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
Table 258. Exception Vector Map and Priority
MM912_634 Advance Information, Rev. 4.0
NOTE
NOTE
Source
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