MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 285

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.39.4.1
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission
begins by writing to the master SPI data register. If the shift register is empty, data immediately transfers to the shift register. Data
begins shifting out on the MOSI pin under the control of the serial clock.
4.39.4.2
The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to
receive the same transmission from a master, although the master would not receive return information from all of the receiving
slaves.
Freescale Semiconductor
•
•
•
•
•
•
Serial clock
The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate
preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the
transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls
the shift register of the slave peripheral.
MOSI, MISO pin
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by
the SPC0 and BIDIROE control bits.
SS pin
If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each
transmission and is high when the SPI is in idle state.
If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input
becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case,
the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO
(or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a
transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable
bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested.
When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started
within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI
clock phase bit, CPHA, in SPI control register 1 (see
Serial clock
In slave mode, SCK is the SPI clock input from the master.
MISO, MOSI pin
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the
SPC0 bit and BIDIROE bit in SPI control register 2.
SS pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS
must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state.
The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high
impedance, and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the
slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave
mode. For these simpler devices, there is no serial data out pin.
Master Mode
Slave Mode
A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN, SPC0, or BIDIROE
with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission
in progress and force the SPI into idle state. The remote slave cannot detect this, therefore
the master must ensure that the remote slave is returned to idle state.
When peripherals with duplex capability are used, take care not to simultaneously enable
two receivers whose serial outputs drive the same system slave’s serial data output line.
MM912_634 Advance Information, Rev. 4.0
NOTE
NOTE
Section 4.39.4.3, “Transmission
Formats”).
285