ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 3

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Contents
1.0
2.0
3.0
4.0
5.0
Datasheet
Document Number: 249414-003
Revision Date: 25-Oct-2005
Introduction to This Document ......................................................................................... 11
1.1
1.2
Block Diagram for Intel
Ball and Pin Assignments for Intel
Signal Descriptions for Intel
Functional Description...................................................................................................... 24
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Document Overview ............................................................................................11
Related Documents............................................................................................. 11
Device Overview .................................................................................................25
5.1.1
5.1.2
Network Media / Protocol Support.......................................................................26
5.2.1
5.2.2
5.2.3
Operating Requirements .....................................................................................32
5.3.1
5.3.2
Initialization.......................................................................................................... 33
5.4.1
5.4.2
5.4.3
5.4.4
Establishing Link .................................................................................................39
5.5.1
5.5.2
MII Operation....................................................................................................... 41
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
100 Mbps Operation ............................................................................................46
5.7.1
5.7.2
5.7.3
10 Mbps Operation.............................................................................................. 55
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
Comprehensive Functionality ................................................................. 25
Optimal Signal Processing Architecture ................................................. 25
10/100 Network Interface .......................................................................26
MII Data Interface ................................................................................... 29
Configuration Management Interface ..................................................... 29
Power Requirements ..............................................................................32
Clock Requirements ............................................................................... 32
MDIO Control Mode and Hardware Control Mode .................................35
Reduced-Power Modes .......................................................................... 35
Reset for Intel
Hardware Configuration Settings ...........................................................37
Auto-Negotiation.....................................................................................39
Parallel Detection ................................................................................... 40
MII Clocks............................................................................................... 42
Transmit Enable .....................................................................................43
Receive Data Valid ................................................................................. 43
Carrier Sense ......................................................................................... 44
Error Signals........................................................................................... 44
Collision .................................................................................................. 44
Loopback................................................................................................ 45
100BASE-X Network Operations ...........................................................46
Collision Indication ................................................................................. 49
100BASE-X Protocol Sublayer Operations ............................................ 50
10BASE-T Preamble Handling ............................................................... 55
10BASE-T Carrier Sense .......................................................................55
10BASE-T Dribble Bits ........................................................................... 55
10BASE-T Link Integrity Test ................................................................. 56
Link Failure ............................................................................................. 56
®
LXT971A Transceiver ............................................................... 12
Intel
®
LXT971A Transceiver........................................................ 17
®
®
LXT971A Transceiver ................................................... 36
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
LXT971A Transceiver.............................................. 13
3