ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 40

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
5.5.1.2
5.5.1.3
5.5.2
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®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Manual Next Page Exchange
“Next Page Exchange” information is additional information that exceeds the information required
by Base Page exchange and that is sent by “Next Pages”. The LXT971A Transceiver fully supports
the IEEE 802.3 standard method of negotiation through the Next Page exchange.
The Next Page exchange uses Register 7 to send information and Register 8 to receive it. Next
Page exchange occurs only if both ends of the link partners advertise their ability to exchange Next
Pages. Register bit 6.1 is used to make manual next page exchange easier for software. This
register bit is cleared when a new negotiation occurs, preventing the user from reading an old value
in Register 6 and assuming there is valid information in Registers 5 and 8.
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, Intel recommends the following steps:
Parallel Detection
In parallel with auto-negotiation, the LXT971A Transceiver also monitors for 10 Mbps Normal
Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device
automatically reverts to the corresponding speed in half-duplex mode. Parallel detection allows the
LXT971A Transceiver to communicate with devices that do not support auto-negotiation.
When parallel detection resolves a link, the link must be established in half-duplex mode.
According to IEEE standards, the forced link partner cannot be configured to full-duplex. If the
auto-negotiation link partner does not advertise half-duplex capability at the speed of the forced
link partner, link is not established. The IEEE Standard prevents full-duplex-to-half-duplex link
connections.
1. After power-up, power-down, or reset, the power-down recovery time (specified in
2. Set the Auto-Negotiation Advertisement Register bits.
3. Enable auto-negotiation. (Set MDIO Register bit 0.12 = 1.)
4. To ensure proper operation, enable or restart auto-negotiation as soon as possible after writing
“Intel® LXT971A Transceiver RESET_L Pulse Width and Recovery Timing” on page
must be exhausted before proceeding.
to Register 4.
Document Number: 249414-003
Revision Date: June 18, 2004
Datasheet
Table 43,
87)