ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 99

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Table 57. Interrupt Enable Register - Address 18, Hex 12
Table 57
18.15:9
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
18.0
1. R/W = Read /Write
Bit
lists interrupt enable bits.
Reserved
Reserved
ANMSK
SPEEDMSK
DUPLEXMSK
LINKMSK
Reserved
Reserved
INTEN
TINT
Name
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Mask for Auto Negotiate Complete
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Speed Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Duplex Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Mask for Link Status Interrupt
0 = Do not allow event to cause interrupt.
1 = Enable event to cause interrupt.
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
Interrupt Enable.
0 = Disable interrupts.
1 = Enable interrupts.
Test Force Interrupt
0 = Normal operation.
1 = Force interrupt on MDINT_L
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
Default
N/A
0
0
0
0
0
0
0
0
0
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