ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 88

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
8.0
88
Table 44. Register Set for IEEE Base Registers
Table 45. Control Register - Address 0, Hex 0 (Sheet 1 of 2)
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Register Definitions - IEEE Base Registers
This chapter includes definitions for the IEEE base registers used by the LXT971A Transceiver.
Chapter 9.0, “Register Definitions - Product-Specific Registers”
product-specific LXT971A Transceiver registers, which are defined in accordance with the IEEE
802.3 standard for adding unique device functions.
The LXT971A Transceiver register set has multiple 16-bit registers.
Table 45
•
•
Address
0.15
0.14
0.13
11 to 14
Bit
Table 44
Table 45
which are defined in accordance with the “Reconciliation Sublayer and Media Independent
Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation” sections of
the IEEE 802.3 standard.
10
15
0
1
2
3
4
5
6
7
8
9
lists control register bits.
Reset
Loopback
Speed Selection
Control Register
Status Register #1
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Next Page Receive Register
1000BASE-T/100BASE-T2 Control Register
1000BASE-T/100BASE-T2 Status Register
Reserved
Extended Status Register
is a register set listing of the IEEE base registers.
through
Name
Table 53
0 = Normal operation
1 = PHY reset
0 = Disable loopback mode
1 = Enable loopback mode
provide bit descriptions of the base registers (address 0 through 8),
0.6
0
0
1
1
Register Name
0.13
0
1
0
1
10 Mbps
100 Mbps
1000 Mbps (not supported)
Reserved
Description
Speed Selected
includes definitions of additional
See
See
See
See
See
See
See
See
See
Not Implemented
Not Implemented
Not Implemented
Not Implemented
Document Number: 249414-003
Table 45
Table 46.
Table 47.
Table 48.
Table 49
Table 50.
Table 51.
Table 52.
Table 53.
Revision Date: June 18, 2004
Bit Assignments
Type
R/W
R/W
R/W
SC
1
Datasheet
Default
Note 2
0
0