ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 32

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Intel
5.3
5.3.1
5.3.2
5.3.2.1
5.3.2.2
32
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Note:
Note:
Operating Requirements
Power Requirements
The LXT971A Transceiver requires three power supply inputs:
The digital and analog circuits require 3.3 V supplies (VCCA and VCCD). These inputs may be
supplied from a single source. Each supply input must be de-coupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either +2.5 V or
+3.3 V. Also, the inputs on the MII interface are tolerant to 5 V signals from the controller on the
other side of the MII interface. For MII I/O characteristics, see
Characteristics1 - MII Pins” on page
Bring up power supplies as close to the same time as possible.
As a matter of good practice, keep power supplies as clean as possible.
Clock Requirements
External Crystal/Oscillator
The LXT971A Transceiver requires a reference clock input that is used to generate transmit signals
and recover receive signals. It may be provided by either of two methods: by connecting a crystal
across the oscillator pins (XI and XO) with load capacitors, or by connecting an external clock
source to pin XI.
The connection of a clock source to the XI pin requires the XO pin to be left open. To minimize
transmit jitter, Intel recommends a crystal-based clock instead of a derived clock (that is, a PLL-
based clock).
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a
crystal, is frequently used in switch applications. For clock timing requirements, see
Characteristics - REFCLK/XI and XO Pins” on page
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. For details, see
MDIO Timing” on page
•
•
•
VCCA
VCCD
VCCIO
85.
72.
73.
Table 41, “Intel® LXT971A Transceiver
Table 23, “Digital I/O
Document Number: 249414-003
Revision Date: June 18, 2004
Table 24, “I/O
Datasheet