SAK-C505CA-4RM CA Infineon Technologies, SAK-C505CA-4RM CA Datasheet - Page 11

• Manufacturer Part Number: SAK-C505CA-4RM CA
• Description: Microcontrollers (MCU) 8-Bit Single Chip Microcontroller
• Manufacturer: Infineon Technologies

Specifications of SAK-C505CA-4RM CA

• Data Bus Width: 8 bit
• Program Memory Type: ROM
• Program Memory Size: 32 KB
• Data Ram Size: 1.25 KB
• Interface Type: USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PG-MQFP-44
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-44
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 1.25 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 32.0 KByte
• Lead Free Status / Rohs Status: No
• Other names: K505CA4RMCANT

Table 2
Pin Definitions and Functions (cont’d)
Symbol
RESET
P3.0-P3.7
*) I = Input
Data Sheet
O = Output
4
5, 7-13
5
7
8
9
10
11
12
13
Pin Number
I/O
*)
I
I/O
Function
RESET
A high level on this pin for two machine cycle while the
oscillator is running resets the device. An internal diffused
resistor to V
external capacitor to V
Port 3
is an 8-bit quasi-bidirectional port with internal pull-up
arrangement. Port 3 pins that have 1’s written to them are
pulled high by the internal pull-up transistors and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup transistors.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to operate
(except for TxD and WR). The secondary functions are
assigned to the pins of port 3 as follows:
P3.0 / RxD
P3.1 / TxD
P3.2 / INT0
P3.3 / INT1
P3.4 / T0
P3.5 / T1
P3.6 / WR
P3.7 / RD
7
SS
permits power-on reset using only an
Receiver data input (asynch.) or data
input/output (synch.) of serial interface
Transmitter data output (asynch.) or
clock output (synch.) of serial interface
External interrupt 0 input / timer 0 gate
control input
External interrupt 1 input / timer 1 gate
control input
Timer 0 counter input
Timer 1 counter input
WR control output; latches the data
byte from port 0 into the external data
memory
RD control output; enables the external
data memory
C505/C505C/C505A/C505CA
DD
.
IL
, in the DC
12.00