SAK-C505CA-4RM CA Infineon Technologies, SAK-C505CA-4RM CA Datasheet - Page 44

• Manufacturer Part Number: SAK-C505CA-4RM CA
• Description: Microcontrollers (MCU) 8-Bit Single Chip Microcontroller
• Manufacturer: Infineon Technologies

Specifications of SAK-C505CA-4RM CA

• Data Bus Width: 8 bit
• Program Memory Type: ROM
• Program Memory Size: 32 KB
• Data Ram Size: 1.25 KB
• Interface Type: USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PG-MQFP-44
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-44
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 1.25 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 32.0 KByte
• Lead Free Status / Rohs Status: No
• Other names: K505CA4RMCANT

10-Bit A/D Converter (C505A and C505CA only)
The C505A/C505CA includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8
analog input channels. It operates with a successive approximation technique and uses self
calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D
converter provides the following features:
The 10-bit ADC uses two clock signals for operation : the conversion clock f
input clock f
XTAL pins. The input clock f
frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which
assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the
bits ADCL1 and ADCL0 of SFR ADCON1.
Figure 19
10-Bit A/D Converter Clock Selection
Data Sheet
– 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors
MCU System Clock
Rate (f
12 MHz
16 MHz
20 MHz
2 MHz
6 MHz
8 MHz
IN
(=1/t
Condition:
f
OSC
OSC
IN
)
). f
f
ADC
ADC max
Clock Prescaler
IN
ADCL1
16
32
is derived from the C505 system clock f
8
4
is equal to f
f
[MHz]
12
16
20
IN
< 2 MHz
2
6
8
MUX
ADCL0
OSC
Prescaler
Ratio
f
Conversion Clock
IN
4
4
4
8
8
16
= f
The conversion f
40
OSC
Input Clock
=
CLP
f
[MHz]
0.5
1.5
2
1.5
2
1.25
1
ADC
C505/C505C/C505A/C505CA
f
ADC
f
IN
ADC
clock is limited to a maximum
ADCL1
0
0
0
0
0
1
OSC
Converter
A / D
MCS03635
which is applied at the
ADC
(=1/t
ADCL0
0
0
0
1
1
0
ADC
) and the
12.00