SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 109
SAA7114HV2
Manufacturer Part Number
SAA7114HV2
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7114HV2.pdf
(144 pages)
Specifications of SAA7114HV2
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Philips Semiconductors
SAA7114_3
Product data sheet
10.5.5 Subaddresses 90h and C0h
Table 96:
[1]
Table 97:
[1]
Table 98:
Table 99:
[1]
Bit
D2
D1
D0
Event handler control
Output field ID is field ID from scaler input
Output field ID is task status flag, which changes every time a
selected task is activated (not synchronized to input field ID)
Scaler SAV/EAV byte bit D7 and task flag = 1, default
Scaler SAV/EAV byte bit D7 and task flag = 0
Event handler control
Active task is carried out directly
1 field is skipped before active task is carried out
... fields are skipped before active task is carried out
6 fields are skipped before active task is carried out
7 fields are skipped before active task is carried out
Event handler control
Event handler triggers immediately after finishing a task
Event handler triggers with next V-sync
Event handler triggers with field ID = 0
Event handler triggers with field ID = 1
If active task is finished, handling is taken over by the next task
Active task is repeated once, before handling is taken over by the next
task
Status information is unsynchronized and shows the actual status at the time of I
X = don’t care.
X = don’t care.
I
status bit
ERROF
FIDSCI
FIDSCO
2
C-bus
Status information scaler part; 8Fh[7:0]; read only register
Task handling control; register set A [90h[7:6]] and B [C0h[7:6]]
Task handling control; register set A [90h[5:3]] and B [C0h[5:3]]
Task handling control; register set A [90h[2:0]] and B [C0h[2:0]]
Function
error flag of scalers output formatter, normally set, if the output processing
needs to be interrupted, due to input/output data rate conflicts, e.g. if
output data rate is much too low and all internal FIFO capacity used
status of the field sequence ID at the scalers input
status of the field sequence ID at the scalers output, scaler processing
dependent
Rev. 03 — 17 January 2006
[1]
PAL/NTSC/SECAM video decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Control bits D7 and D6
CONLH
X
X
0
1
Control bits D5 to D3
FSKP2
0
0
...
1
1
Control bits D2 to D0
RPTSK STRC1 STRC0
X
X
X
X
0
1
…continued
2
C-bus read.
FSKP1
0
0
...
1
1
SAA7114
[1]
[1]
0
0
1
1
X
X
OFIDC
0
1
X
X
FSKP0
0
1
...
0
1
109 of 144
0
1
0
1
X
X
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