SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 86
SAA7114HV2
Manufacturer Part Number
SAA7114HV2
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7114HV2.pdf
(144 pages)
Specifications of SAA7114HV2
Lead Free Status / Rohs Status
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Philips Semiconductors
SAA7114_3
Product data sheet
10.2.4 Subaddress 03h
Table 41:
Bit
D6
D5
D4
Fig 46. Mode 4 CVBS (automatic gain)
Fig 48. Mode 6 Y+ C (gain channel 2
Fig 50. Mode 8 Y+ C (gain channel 2
AI24
AI23
AI22
AI21
AI24
AI23
AI22
AI21
AI24
AI23
AI22
AI21
AI12
AI11
AI12
AI11
AI12
AI11
Description
HL not reference select HLNRS
AGC hold during
vertical blanking period
white peak control off
I
bit D7) should be set to logic 1 (full
luminance bandwidth).
adjusted via GAI2)
I
bit D7) should be set to logic 1 (full
luminance bandwidth).
adapted to Y gain)
2
2
C-bus bit BYPS (subaddress 09h,
C-bus bit BYPS (subaddress 09h,
Analog input control 2 (AICO2); 03h[6:0]
AD2
AD1
AD2
AD1
AD2
AD1
Rev. 03 — 17 January 2006
Symbol Value
VBSL
WPOFF 0
CHROMA
LUMA
CHROMA
LUMA
CHROMA
LUMA
mhb563
mhb565
mhb567
0
1
0
1
1
[1]
[1]
Function
normal clamping if decoder is in unlocked state
reference select if decoder is in unlocked state
short vertical blanking (AGC disabled during
equalization and serration pulses)
long vertical blanking (AGC disabled from start
of pre-equalization pulses until start of active
video (line 22 for 60 Hz, line 24 for 50 Hz)
white peak control active
white peak control off
Fig 47. Mode 5 CVBS (automatic gain)
Fig 49. Mode 7 Y+ C (gain channel 2
Fig 51. Mode 9 Y+ C (gain channel 2
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AI11
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I
bit D7) should be set to logic 1 (full
luminance bandwidth).
adjusted via GAI2)
I
bit D7) should be set to logic 1 (full
luminance bandwidth).
adapted to Y gain)
PAL/NTSC/SECAM video decoder
2
2
C-bus bit BYPS (subaddress 09h,
C-bus bit BYPS (subaddress 09h,
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
AD2
AD2
AD2
AD1
AD1
AD1
SAA7114
CHROMA
LUMA
CHROMA
LUMA
CHROMA
LUMA
86 of 144
mhb564
mhb566
mhb568
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