SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 31
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SAA7114HV2
Manufacturer Part Number
SAA7114HV2
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7114HV2.pdf
(144 pages)
Specifications of SAA7114HV2
Lead Free Status / Rohs Status
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Philips Semiconductors
SAA7114_3
Product data sheet
8.1.4 Synchronization
8.1.5 Clock generation circuit
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is
further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the
phase detectors where they are compared with the sub-divided clock frequency. The
resulting output signal is applied to the loop filter to accumulate all phase deviations.
Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to generate the line frequency
control signal LFCO; see
The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is
also achieved within the synchronization circuit.
The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh.
The internal CGC generates all clock signals required for the video input processor.
The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal
PLL. It is the multiple of the line frequency:
The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including
phase detector, loop filtering, VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50 % duty factor.
Fig 19. CVBS (raw data) range for scaler input, data slicer and X port output
•
•
6.75 MHz = 429
6.75 MHz = 432
a. Sources containing 7.5 IRE black level
CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128.
Equation for modification of the raw data levels via bytes RAWG and RAWO:
It should be noted that the resulting levels are limited to 1 to 254 in accordance with
“ITU Recommendation 601/656” .
offset (e.g. NTSC M).
255
209
CVBS
71
60
1
OUT
LUMINANCE
SYNC
=
Int
Rev. 03 — 17 January 2006
f
f
H
H
RAWG
-----------------
(50 Hz), or
(60 Hz)
Figure
black
black shoulder
sync bottom
64
white
001aac244
20.
CVBS
nom
–
128
+
b. Sources not containing black level
255
199
RAWO
60
1
offset.
PAL/NTSC/SECAM video decoder
LUMINANCE
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SYNC
white
black shoulder = black
sync bottom
SAA7114
001aac245
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