PCA9575PW2,118 NXP Semiconductors, PCA9575PW2,118 Datasheet - Page 12

• Manufacturer Part Number: PCA9575PW2,118
• Description: IC I2C/SMBUS 16BIT GPIO 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of PCA9575PW2,118

• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Includes: POR
• Description/function: 16-bit I2C-bus and SMBus
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286414118

NXP Semiconductors
PCA9575_3
Product data sheet
7.6.4 Register 3 - Polarity inversion port 1 register
7.6.5 Register 4 - Bus-hold/pull-up/pull-down enable 0 register
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 7.
Legend: * default value.
Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 0. In this mode, the
pull-up/pull-downs will be disabled for I/O bank 0. Setting the bit 0 to logic 0 disables
bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 6. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 0 pins and contents of
Register 6 will have no effect on the I/O.
Table 8.
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Symbol
E0.7
E0.6
E0.5
E0.4
E0.3
E0.2
E0.1
E0.0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Register 3 - Polarity Inversion port 1 register (address 03h) bit description
Register 4 - Bus-hold/pull-up/pull-down enable 0 register (address 04h)
bit description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 03 — 9 November 2009
16-bit I
Value Description
X
X
X
X
X
X
0*
0*
Value
0*
0*
0*
0*
0*
0*
0*
0*
2
C-bus and SMBus, level translating, low voltage GPIO
not used
allows the user to enable/disable pull-up/pull-downs on the
I/O bank 0 pins
allows user to enable/disable the bus-hold feature for the
I/O bank 0 pins
0 = disables pull-up/pull-downs on the I/O bank 0 pins and
contents of Register 6 will have no effect on the I/O bank 0
(default value)
1 = enables selection of pull-up/pull-down using Register 6
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature
Description
inverts polarity of Input port 1 register data
0 = Input port 1 register data retained (default value)
1 = Input port 1 register data inverted
PCA9575
© NXP B.V. 2009. All rights reserved.
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