AD9929BBCZ Analog Devices Inc, AD9929BBCZ Datasheet - Page 11

• Manufacturer Part Number: AD9929BBCZ
• Description: IC CCD SIGNAL PROCESSOR 64-BGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9929BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 8. Control Register Address Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
Content
(23:0)
23
(22:21)
(20:18)
17
16
(15:14)
13
(12:10)
(9:8)
7
6
5
4
(3:1)
0
(23:22)
(21:16)
(15:14)
(13:8)
(7:6)
(5:0)
(23:17)
16
(15:14)
(13:8)
(7:6)
(5:0)
(23:16)
15
(14:12)
11
(10:8)
(7:3)
(2:0)
(23:10)
9
8
(7:2)
1
0
Bit
Width
24
1
2
3
1
1
2
1
3
2
1
1
1
1
3
1
2
6
2
6
2
6
7
1
2
6
2
6
8
1
3
1
3
5
3
14
1
1
6
1
1
Default
Value
000000
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0x34
0
0x18
0
0x0B
0x00
0
0
0x00
0
0x10
0x80
–
5
0
5
0x00
2
0x0000
0
0
00
0
1
Register Name
SW_RESET
Unused
XSUBCKSUPPRESS
Unused
HBLKMASK
SYNCPOL
Unused
XSUBCKMODE_HP
Unused
MSHUTPAT
MSHUT/VGATE_EN
Unused
CLPOB_CONT
CLPOB_MODE
Unused
VDMODE
Unused
SHDLOC
Unused
SHPLOC
DCLKPHASE
DOUTPHASE
Unused
H1BLKRETIME
Unused
H1POSLOC
Unused
RGNEGLOC
REFBLACK
Unused
H2DRV
Unused
H1DRV
Unused
RGDRV
Unused
AFESTBY
DIGSTBY
Unused
OUTCONT_REG
OUTCONT_ENB
Rev. A | Page 11 of 64
Register Description
Software Reset = 000000 (Reset All Registers to Default )
Suppress XSUBCK (00 = No Suppression, 01 = Suppress First XSUBCK
After Last VSG Line Pulse, 10 = Suppress All XSUBCKs, Except Final
XSUBCK, 11 = No Suppression)
Test Mode. Should Be Set = 0
Masking Polarity for H1 During Blanking Period (0 = Low, 1 = High)
External SYNC Active Polarity (0 = Active Low)
High Precision Shutter Mode Operation
(0 = Single Pulse, 1 = Multiple Pulse)
Selects MSHUT Pattern. (See Figure 51)
(0 = Mshutpat0,1 = Mshutpat1,2 = Mshutpat2, 3 = Mshutpat3)
MSHUT Masking of VGATE Input (0 = MSHUT Does Not Mask VGATE,
1 = MSHUT Does Mask VGATE)
CLPOB Control (0 = CLPOB Off, 1 = CLPOB On)
CLPOB CCD Region Control (See Table 19)
VD Synchronous/Asynchronous Mode Setting
(0 = VD Synchronous, 1 = VD Asynchronous )
SHD Sample Location
SHP Sample Location
DCLK Pulse Adjustment
Data Output [11:0] Phase Adjustment
Retimes the H1 HBLK to Internal Clock
H1 Positive Edge Location
RG Negative Edge Location
Black Level Clamp
H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA,
4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA)
AFE Standby (0 = Standby, 1 = Normal Operation)
Digital Standby (0 = Standby, 1 = Normal Operation)
Internal OUTCONT Signal Control
(0 = Digital Outputs Held at Fixed DC Level, 1 = Normal Operation)
External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled,
1 = Pin Disabled)
AD9929