AD9929BBCZ Analog Devices Inc, AD9929BBCZ Datasheet - Page 28

• Manufacturer Part Number: AD9929BBCZ
• Description: IC CCD SIGNAL PROCESSOR 64-BGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9929BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9929
HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING
The HD and VD output pulses are programmable using the
registers listed in Table 18. The HD output is asserted low at the
start of the horizontal line shift. The VD output is asserted low
at the start of each line. As shown in Figure 22, the 11-bit VD
counter is used to count the number of lines set by the VDLEN
register. The 12-bit HD counter is used to count the number of
pixels in each line set by the HDLEN register. For example, if
the CCD array size is 2000 lines by 2100 pixels per line,
VDLEN = 2000 and HDLEN = 0xC28. The HDLEN register
sets HL as a reference for the rising edge of the HD pulse.
Table 18. HD and VD Registers
Register Name
HDLEN
HLEN
HDRISE
HDLASTLEN
VDLEN
VDRISE
1
Register value must be a gray code number (see Gray Code Registers section).
1
1
GRAY COUNTER
VD COUNTER
HL COUNTER
+ SET- UP
11-BIT
12-BIT
10-BIT
Bit
Width
12
10
10
12
11
4
VD
HD
NOTES
1. THE SET-UP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4 MORE CYCLES
2. VDRISE REFERENCES THE 11-BIT VD-COUNTER.
3. HDRISE REFERENCES THE 10-BIT HL-CONTER.
PROGRAMMABLE CLOCK POSITIONS
1. HDRISE (SYS_REG(16))
2. VDRISE (SYS_REG(16))
THAN VALUE SET IN HDLEN AND HDLASTLEN DUE TO SET-UP DELAY.
HLEN
Register Type
Sys_Reg(12)
Sys_Reg(12)
Sys_Reg(16)
Mode_Reg(1)
Mode_Reg(1)
Sys_Reg(16)
1
LINE LENGTH =
HDLEN + 4
HDLEN
000
Figure 22. VD and HD Horizontal Timing
Reference
Counter
–
–
HL
HD
–
VD
Rev. A | Page 28 of 64
001
2
Range
0–4095 Pixels
0–1023 Pixels
0–1023 Pixels
0–4095 Pixels
0–2047 Lines
0–15 Lines
SPECIAL NOTE ABOUT THE HDLEN REGISTER
The 12-bit HD counter value must be programmed using a gray
code number. There is also a 4-clock cycle, set up period that
must be considered when determining the HDLEN register
value, as shown in Figure 22. As a result of the 4-clock cycle,
setup period, the value of HDLEN is always equal to the actual
number of pixels per line minus 4. For example, if there are
2100 pixels per line, HDLEN equals (2100 – 4) = 2096. The gray
code value of 2096 is 0xC28, which is what would be program-
med in the HDLEN register.
VDLEN
002
Description
12-Bit Gray Code Counter Value
10-Bit HL-Counter Value
HD Rise Position
HD Last Line Length
VD Counter Value
VD Rise Position
HDLASTLEN
N _ < 2048