FIN212ACGFX Fairchild Semiconductor, FIN212ACGFX Datasheet - Page 6

• Manufacturer Part Number: FIN212ACGFX
• Description: IC SER/DESER 12BIT 42USS-BGA
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN212ACGFX

• Function: Serializer/Deserializer
• Data Rate: 560Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 12
• Number Of Outputs: 12
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 42-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN212ACGFXTR

Application Diagrams
The following application diagrams illustrate the most typical applications for the FIN212 device. Specific configurations of the
control pins may vary based on the needs of a given system. The following recommendations are valid for all of the
applications shown.
© 2008 Fairchild Semiconductor Corporation
FIN212AC • Rev. 1.1.0
Baseband
Processor
Baseband
Processor
PIXEL CLK
PIXEL CLK
Data[7:0]
HSYNC
VSYNC
YUV[7:0]
HSYNC
VSYNC
/RES
/RES
Serializer Configuration:
8MHz to 28MHz Frequency Range (S1=S0=1)
Normal Mode (PLL1=0; PLL0=1)
Deserializer Configuration:
~2 – 3ns output edge rates (S1=0, S0=1)
~50% CKP PW,(PWS1=PWS0=0)
Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package)
NC
VDDP1
NC
B3:E1
E2
F1
G1:F2
B3:E1
E2
F1
G1:F2
Figure 4. 8-Bit RGB Application (Example Shows BGA 42-Pin Package)
A6
B5
C1
A6
B5
C1
F6
G3
G4
A3
G5
G6
F6
G3
G4
A4
G5
G6
CKP
CKREF
STROBE
DP[8:1]
DP[9]
DP[10]
DP[12:11]
DIRI
PWS1
PWS0
XTRM
S1
S0
D3
CKREF
STROBE
CKP
DP[8:1]
DP[9]
DP[10]
DP[12:11]
DIRI
PLL1
PLL0
CTL_ADJ
S1
S0
D3
VDDP1
VDDP
VDDP1
VDDP
Deserializer
FIN212AC
FIN212AC
Serializer
GND
GND
E4
VDDS/A
CKSO+
CKSO-
CKSI+
/DIRO
VDDS/A
CKSI-
E4
DSI+
CKSO+
DSI-
CKSO-
CKSI+
DSO+
/DIRO
CKSI-
DSO-
F4
F4
C5
C6
D5
D6
E6
E5
B6
NC
C5
C6
D6
D5
E6
E5
B6
NC NC
NC NC
VDD
NC
NC
NC
NC
VDD
E5
E6
D6
D5
C6
C5
B6
NC
NC
NC
E5
E6
D5
D6
CKSI+
CKSI-
DSO+
DSO-
CKSO-
CKSO+
/DIRO
C6
C5
B6
E4
VDDS/A
6
CKSI+
CKSI-
DSI+
DSI-
CKSO-
CKSO+
/DIRO
FIN212AC
Deserializer Configuration:
~4 – 5ns output edge rates (S1=S0=1)
~50% CKP PW,(PWS1=PWS0=0)
Serializer
Serializer Configuration:
20MHz to 40MHz Frequency Range (S1=0, S0=1)
Normal Mode (PLL1=0, PLL0=1)
E4
VDDS/A
GND
F4
Deserializer
FIN212AC
DP[12:11]
CTL_ADJ
STROBE
VDDP
GND
CKREF
DP[8:1]
F4
VDDP2
DP[10]
DP[9]
D3
PLL1
PLL0
CKP
DIRI
DP[12:11]
STROBE
S1
S0
VDDP
CKREF
DP[8:1]
VDDP2
DP[10]
XTRM
PWS1
PWS0
DP[9]
F6
G3
G4
A4
G5
G6
D3
CKP
DIRI
C1
A6
B5
B3:E1
E2
F1
G1:F2
S1
S0
NC
VDDP2
A3
F6
G3
G4
G5
G6
C1
A6
B5
B3:E1
E2
F1
G1:F2
NC
MASTER CLK
PIXEL CLK
YUV[7:0]
HSYNC
VSYNC
/RES
PIXEL CLK
Data[7:0]
HSYNC
VSYNC
/RES
LCD MODULE
Camera Module
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