AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 62
AN983B-BG-T-V8
Manufacturer Part Number
AN983B-BG-T-V8
Description
IC PCI TO ETHERNET LAN 128-PQFP
Manufacturer
Infineon Technologies
Datasheet
1.AN983B-BG-T-V8.pdf
(116 pages)
Specifications of AN983B-BG-T-V8
Applications
Ethernet Controller
Interface
USB
Voltage - Supply
3 V ~ 3.6 V
Package / Case
128-BFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AN983BBGTV8
SP000074652
SP000074652
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AN983B-BG-T-V8
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Field
Res
MM
PR
SBC
Res
PB
Res
SR
Res
Interrupt Enable Register
IER_CSR7
Interrupt Enable Register
Data Sheet
Bits
9:8
7
6
5
4
3
2
1
0
Type
ro
rw***
rw***
rw**
ro
rw***
ro
rw
ro
Description
Reserved
Multicast Mode
Note: w*** = only write when the receive processor stoppes.
1
Promiscuous Mode
Note: w*** = only write when the receive processor stoppes.
0
1
Stop Back-off Counter
Note: w** = only write when the transmit and receive processor both stop.
0
1
Reserved
Pass Bad Packet
Note: w*** = only write when the receive processor stoppes.
0
1
Reserved
Start/Stop Receive
0
1
Reserved
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
B
B
B
B
B
B
B
carrier drop.
packets, CRC error, truncated packets... For receiving all bad
packets, the bit 6 of CSR6 should be set to 1.
frame has completed. This value is effective only when the receive
processor is in the running or suspending state. Notice: In “Stop
Receive” state the PAUSE packet and Remote Wake Up packet
won’t be affected and can be received if the corresponding function
is enabled.
, receive all multicast packets
, receive only the right destination address packets
, receive any good packet
, back-off counter is not effected by carrier
, back-off counter stop when carrier is active and resume when
, filters all bad packets
, receives any packets if pass address filter, including small
, receive processor will enter stop state after the current reception
, receive processor will enter running state
Offset
38
62
H
Rev. 1.81, 2005-12-15
AN983B/BX
Reset Value
0000 0000
H
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