OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 18

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
LPC122X
Objective data sheet
7.5.2 Interrupt sources
7.6.1 Features
7.7.1 Features
7.6 IOCONFIG block
7.7 Micro DMA controller
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 55 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, a rising edge or falling edge, or both.
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
The micro DMA controller enables memory-to-memory, memory-to-peripheral, and
peripheral-to-memory data transfers. The supported peripherals are: UART0 (transmit
and receive), UART1 (transmit and receive), SSP/SPI (transmit and receive), ADC, RTC,
32-bit counter/timer 0 (match output channels 0 and 1), 32-bit counter/timer 1 (match
output channels 0 and 1), 16-bit counter/timer 0 (match output channel 0), 16-bit
counter/timer 1 (match output channel 0), comparator 0, comparator 1, GPIO0 to GPIO2.
•
•
•
•
•
•
•
•
•
•
•
•
•
In the LPC122x, the NVIC supports 32 vectored interrupts. In addition, up to 12 of the
individual GPIO inputs are NVIC-vector capable.
Four programmable interrupt priority levels with hardware priority level masking.
Software interrupt generation.
Non-maskable Interrupt (NMI) can be programmed to use any of the peripheral
interrupts. The NMI is not available on an external pin.
Programmable pull-up resistor.
Programmable digital glitch filter.
Programmable input inverter.
Programmable drive current.
Programmable open-drain mode.
Single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit
data bus.
21 DMA channels.
Handshake signals and priority level programmable for each channel.
Each priority level arbitrates using a fixed priority that is determined by the DMA
channel number.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 29 March 2011
32-bit ARM Cortex-M0 microcontroller
LPC122x
© NXP B.V. 2011. All rights reserved.
18 of 60