OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 22

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
LPC122X
Objective data sheet
7.15.1 Features
7.16.1 Features
7.15 General purpose external event counter/timers
7.16 Windowed WatchDog timer (WWDT)
The LPC122x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes up to four capture inputs to trap the
timer value when an input signal transitions, optionally generating an interrupt.
The purpose of the watchdog is to reset the microcontroller within a windowed amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Comparator outputs connect to two timers, allowing for the recording of comparison
event time stamps.
A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
Counter or timer operation.
Up to four capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
Supports timed DMA requests.
Internally resets chip if not periodically reloaded.
Debug mode.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Safe operation: can be locked by software to be always on.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 29 March 2011
32-bit ARM Cortex-M0 microcontroller
LPC122x
© NXP B.V. 2011. All rights reserved.
22 of 60