OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 21
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
NXP Semiconductors
LPC122X
Objective data sheet
7.13.1 Features
7.14.1 Features
7.13 10-bit ADC
7.14 Comparator block
The LPC122x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
The comparator block consists of two analog comparators.
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Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The I
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to V
10-bit conversion time of 257 kHz.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or counter/timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
Up to six selectable external sources per comparator; fully configurable on either
positive or negative comparator input channels.
BOD 0.9 V internal reference voltage selectable on both comparators; configurable on
either positive or negative comparator input channels.
32-stage Voltage Ladder internal reference voltage selectable on both comparators;
configurable on either positive or negative comparator input channels.
Voltage ladder source voltage is selectable from an external pin or an internal 3.3 V
voltage rail if external power source is not available.
Voltage ladder can be separately powered down for applications only requiring the
comparator function.
Relaxation oscillator circuitry output for a feedback 555-style timer application.
Common interrupt connected to NVIC.
Comparator outputs selectable as synchronous or asynchronous.
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C-bus can be used for test and diagnostic purposes.
C-bus controller supports multiple address recognition and a bus monitor mode.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 29 March 2011
DD(3V3)
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32-bit ARM Cortex-M0 microcontroller
LPC122x
© NXP B.V. 2011. All rights reserved.
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