OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 9
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
NXP Semiconductors
Table 3.
LPC122X
Objective data sheet
Symbol
PIO0_7/CTS0/
CT32B1_CAP1/
CT32B1_MAT1
PIO0_8/RXD1/
CT32B1_CAP2/
CT32B1_MAT2
PIO0_9/TXD1/
CT32B1_CAP3/
CT32B1_MAT3
PIO0_10/SCL
PIO0_11/SDA/
CT16B0_CAP0/
CT16B0_MAT0
PIO0_12/CLKOUT/
CT16B0_CAP1/
CT16B0_MAT1
RESET/PIO0_13
PIO0_14/SCK
PIO0_15/SSEL/
CT16B1_CAP0/
CT16B1_MAT0
PIO0_16/MISO/
CT16B1_CAP1/
CT16B1_MAT1
LPC122x pin description
25 37
28 40
29 41
30 42
22 26
23 27
24 28
26 38
27 39
31 43
[2]
[2]
[2]
[3]
[3]
[7]
[4]
[2]
[2]
[2]
Start
logic
input
yes
yes
yes
yes
yes
no
no
no
no
no
…continued
All information provided in this document is subject to legal disclaimers.
Type Reset
I/O
I
I
O
I/O
I
I
O
I/O
O
I
O
I/O
I/O
I/O
I/O
I
O
I/O
O
I
O
I
I/O
I/O
I/O
I/O
I/O
I
O
I/O
I/O
I
O
Rev. 1.2 — 29 March 2011
state
[1]
I; PU
-
-
-
I; PU
-
-
-
I; PU
-
-
-
I; IA
-
I; IA
-
-
-
I; PU
-
-
-
I; PU
-
I; PU
-
I; PU
-
-
-
I; PU
-
-
-
Description
PIO0_7 — General purpose digital input/output pin.
CTS0 — Clear To Send input for UART0.
CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.
CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.
PIO0_8 — General purpose digital input/output pin.
RXD1 — Receiver input for UART1.
CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.
CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.
PIO0_9 — General purpose digital input/output pin.
TXD1 — Transmitter output for UART1.
CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1.
CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.
PIO0_10 — General purpose digital input/output pin.
SCL — I
PIO0_11 — General purpose digital input/output pin.
SDA — I
CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.
CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.
PIO0_12 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
High-current output driver.
CLKOUT — Clock out pin.
CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.
CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.
RESET — External reset input: A LOW on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
PIO0_13 — General purpose digital input/output pin.
PIO0_14 — General purpose digital input/output pin.
SCK — Serial clock for SSP/SPI.
PIO0_15 — General purpose digital input/output pin.
SSEL — Slave select for SSP/SPI.
CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1.
CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1.
PIO0_16 — General purpose digital input/output pin.
MISO — Master In Slave Out for SSP/SPI.
CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1.
CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1.
2
2
C-bus clock input/output.
C-bus data input/output.
32-bit ARM Cortex-M0 microcontroller
LPC122x
© NXP B.V. 2011. All rights reserved.
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