OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 19
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
NXP Semiconductors
LPC122X
Objective data sheet
7.8.1 Features
7.9.1 Features
7.10 UARTs
7.8 CRC engine
7.9 Fast general purpose parallel I/O
The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
The LPC122x contains two UARTs. UART0 supports full modem control and RS-485/9-bit
mode and allows both software address detection and automatic hardware address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
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Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory
transfers.
Supports multiple DMA cycle types and multiple DMA transfer widths.
Performs all DMA transfers using the single AHB-Lite burst type.
Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x
– CRC-16: x
– CRC-32: x
Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
Programmable seed number setting.
Supports CPU programmed I/O or DMA back-to-back transfer.
Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation
– 16-bit write: 2-cycle operation (8-bit 2-cycle)
– 32-bit write: 4-cycle operation (8-bit 4-cycle)
Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
All information provided in this document is subject to legal disclaimers.
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32-bit ARM Cortex-M0 microcontroller
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LPC122x
© NXP B.V. 2011. All rights reserved.
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