KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 158
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
KIT_TC1797_SK
Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr
Datasheets
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
2.KIT_TC1791_SK.pdf
(46 pages)
3.KIT_TC1797_SK.pdf
(101 pages)
4.KIT_TC1797_SK.pdf
(12 pages)
Specifications of KIT_TC1797_SK
Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
- SAK-TC1797-512F180E_AC PDF datasheet
- KIT_TC1791_SK PDF datasheet #2
- KIT_TC1797_SK PDF datasheet #3
- KIT_TC1797_SK PDF datasheet #4
- Current page: 158 of 190
- Download datasheet (6Mb)
4) Applicable for input pins TESTMODE and TRST.
5)
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
9) The duration of the boot time is defined between the following events:
Figure 26
Data Sheet
TESTMODE
f
user instruction has entered the CPU and its processing starts.
1. Hardware reset: the falling edge of a short ESR0 pulse and the moment when the first user instruction has
entered
SCU_RSTCNTCON.RELSA ×
If the ESR0 pulse is longer than SCU_RSTCNTCON.RELSA ×
the boot time (ESR0 falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
FPI
HWCFG
PORST
=
VDDP
TRST
ESR0
Pads
VDD
f
CPU
V
D D PPA
/2
the
Power, Pad and Reset Timing
Pad-state undefined
Tri-state or pull device active
As programmed
CPU
t
POA
t
POA
and
t
hd
t
PIP
T
t
POH
its
FPI
t
t
HDH
PI
.
processing
t
PIP
t
PI
154
starts,
t
hd
t
PIP
if
t
POH
t
t
T
HDH
PI
FPI
the
, only the time beyond should be added to
ESR0
t
t
HDH
PI
Electrical Parameters
pulse
t
PI
V
D D
-12%
is
V1.1, 2009-04
shorter
V
TC1797
D D P
V
reset_beh2
D D PPA
-12%
than
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