M58WR032KU70ZA6U NUMONYX, M58WR032KU70ZA6U Datasheet - Page 18

• Manufacturer Part Number: M58WR032KU70ZA6U
• Description: NUMM58WR032KU70ZA6U NUM 32MB NOR FLASH P
• Manufacturer: NUMONYX

Signal descriptions
2.7
2.8
2.9
2.10
2.11
2.12
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Reset/Power-Down (RP)
The Reset/Power-Down input provides a hardware reset of the memory, and/or power-down
functions, depending on the settings in the Configuration Register. When Reset/Power-
Down is at V
current consumption is reduced to the Standby Supply Current I
Down Supply Current I
characteristics -
Locked state and the bits of the Configuration Register are reset except for Power-Down bit
CR5. When Reset/Power-Down is at V
mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable
or Latch Enable is required to ensure valid data outputs.
Latch Enable (L)
Latch Enable latches the ADQ0-ADQ15 and A16-Amax address bits on its rising edge. The
address latch is transparent when Latch Enable is at V
Enable is at V
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V
read and in write operations.
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at V
at V
The WAIT signal is forced deasserted when Output Enable is at V
Bus Invert (BINV)
Bus invert is an input/output signal used to reduce the amount of power required to switch
the external address/data bus. Power is saved by inverting the data on ADQ0-ADQ15 each
time the inversion results in a reduced number of pin transitions. Data is inverted when BINV
is at V
impedance when Chip Enable or Output Enable is at V
V
V
V
power supply for all operations (Read, Program and Erase).
IL
DD
DD
.
IL
provides the power supply to the internal core of the memory device. It is the main
. It can be configured to be active during the wait cycle or one clock cycle in advance.
IH
supply voltage
(i.e. if the data is AAAAh and BINV is at V
IL
IH
, the memory is in reset mode: the outputs are high impedance and the
.
currents, for the value of I
DD2
if the Power-Down function is enabled. Refer to
IH
, the device is in normal operation. Exiting reset
DD2
and I
IL
IH
. Clock is don't care during asynchronous
DD3
, AAAAh becomes 5555h). BINV is high
IL
IH
. After reset all blocks are in the
and it is inhibited when Latch
or when Reset/Power Down is at
M58WRxxxKU, M58WRxxxKL
DD3
IH
, or to the Reset/Power-
.
Table 22: DC
IH
or Reset is