M58WR032KU70ZA6U NUMONYX, M58WR032KU70ZA6U Datasheet - Page 9

• Manufacturer Part Number: M58WR032KU70ZA6U
• Description: NUMM58WR032KU70ZA6U NUM 32MB NOR FLASH P
• Manufacturer: NUMONYX

M58WRxxxKU, M58WRxxxKL
1
Description
The M58WR016KU/L, M58WR032KU/L and M58WR064KU/L are 16-Mbit (1 Mbit × 16), 32-
Mbit (2 Mbit × 16) and 64-Mbit (4 Mbit × 16) non-volatile Flash memories, respectively. In the
rest of the document, they will be referred to as M58WRxxxKU/L unless otherwise specified.
The M58WRxxxKU/L may be erased electrically at block level and programmed in-system
on a Word-by-Word basis using a 1.7 V to 2 V V
V
speed up customer programming.
The first sixteen address lines are multiplexed with the Data Input/Output signals on the
multiplexed address/data bus ADQ0-ADQ15. The remaining address lines, A16-Amax, are
the Most Significant Bit addresses.
The device features an asymmetrical block architecture:
●
●
●
The Multiple Bank Architecture allows Dual Operations, while programming or erasing in
one bank, Read operations are possible in other banks. Only one bank at a time is allowed
to be in Program or Erase mode. It is possible to perform burst reads that cross bank
boundaries. The bank architectures are summarized in Tables 2,
maps are shown in Figures 3,
memory address space for the M58WR016KU, M58WR032KU and M58WR064KU, and at
the bottom for the M58WR016KL, M58WR032KL and M58WR064KL.
Each block can be erased separately. Erase can be suspended, in order to perform program
in any other block, and then resumed. Program can be suspended to read data in any other
block and then resumed. Each block can be programmed and erased over 100,000 cycles
using the supply voltage V
available to speed up programming.
Program and Erase commands are written to the Command Interface of the memory. An
internal Program/Erase Controller takes care of the timings necessary for program and
erase operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports synchronous burst read and asynchronous read from all blocks of the
memory array; at power-up the device is configured for asynchronous read. In synchronous
burst mode, data is output on each clock cycle at frequencies of up to 86 MHz. The
synchronous burst read operation can be suspended and resumed.
DDQ
the M58WR016KU/L have an array of 39 blocks, and are divided into 4 Mbit banks.
There are 3 banks each containing 8 main blocks of 32 Kwords, and one parameter
bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
the M58WR032KU/L have an array of 71 blocks, and are divided into 4 Mbit banks.
There are 7 banks each containing 8 main blocks of 32 Kwords, and one parameter
bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
the M58WR064KU/L have an array of 135 blocks, and are divided into 4 Mbit banks.
There are 15 banks each containing 8 main blocks of 32 Kwords, and one parameter
bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
supply for the Input/Output pins. An optional 9 V V
DD
. There are two Enhanced Factory programming commands
4
and 5. The Parameter Blocks are located at the top of the
DD
supply for the circuitry and a 1.7 V to 2 V
PP
power supply is provided to
3
and 4, and the memory
Description
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