M58WR032KU70ZA6U NUMONYX, M58WR032KU70ZA6U Datasheet - Page 34

• Manufacturer Part Number: M58WR032KU70ZA6U
• Description: NUMM58WR032KU70ZA6U NUM 32MB NOR FLASH P
• Manufacturer: NUMONYX

Command interface - Factory program commands
6.3.2
6.3.3
6.3.4
34/123
Program Phase
The Program Phase requires n+1 cycles, where n is the number of words (refer to
Factory Program commands
Three successive steps are required to issue and execute the Program Phase of the
command.
1.
2.
3.
The memory is now set to enter the Verify Phase.
Verify Phase
The Verify Phase is similar to the Program Phase in that all words must be resent to the
memory for them to be checked against the programmed data. The Program/Erase
Controller checks the stream of data with the data that was programmed in the Program
Phase and reprograms the memory location if necessary.
Three successive steps are required to execute the Verify Phase of the command.
1.
2.
3.
If the Verify Phase is successfully completed the memory remains in Read Status Register
mode. If the Program/Erase Controller fails to reprogram a given location, the error will be
signaled in the Status Register.
Exit Phase
Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has returned to Read
mode. A full Status Register check should be done to ensure that the block has been
successfully programmed. See the section on the Status Register for more details.
Use one Bus Write operation to latch the Start Address and the first word to be
programmed. The Status Register Bank Write Status bit SR0 should be read to check
that the P/E.C. is ready for the next word.
Each subsequent word to be programmed is latched with a new Bus Write operation.
The address can either remain the Start Address, in which case the P/E.C. increments
the address location or the address can be incremented in which case the P/E.C.
jumps to the new address. If any address that is not in the same block as the Start
Address is given with data FFFFh, the Program Phase terminates and the Verify Phase
begins. The Status Register bit SR0 should be read between each Bus Write cycle to
check that the P/E.C. is ready for the next word.
Finally, after all words have been programmed, write one Bus Write operation with data
FFFFh to any address outside the block containing the Start Address, to terminate the
programming phase.
Use one Bus Write operation to latch the Start Address and the first word, to be
verified. The Status Register bit SR0 should be read to check that the Program/Erase
Controller is ready for the next word.
Each subsequent word to be verified is latched with a new Bus Write operation. The
words must be written in the same order as in the Program Phase. The address can
remain the Start Address or be incremented. If any address that is not in the same
block as the Start Address is given with data FFFFh, the Verify Phase terminates.
Status Register bit SR0 should be read to check that the P/E.C. is ready for the next
word.
Finally, after all words have been verified, write one Bus Write operation with data
FFFFh to any address outside the block containing the Start Address, to terminate the
Verify Phase.
and
Figure 28: Enhanced Factory Program
M58WRxxxKU, M58WRxxxKL
flowchart).
Table 9: