M58WR032KU70ZA6U NUMONYX, M58WR032KU70ZA6U Datasheet - Page 43

• Manufacturer Part Number: M58WR032KU70ZA6U
• Description: NUMM58WR032KU70ZA6U NUM 32MB NOR FLASH P
• Manufacturer: NUMONYX

M58WRxxxKU, M58WRxxxKL
8.3
8.4
8.5
8.6
X-Latency bits (CR13-CR11)
The X-Latency bits are used during Synchronous Read operations to set the number of
clock cycles between the address being latched and the first data becoming available. Refer
to
For correct operation the X-Latency bits can only assume the values in
Configuration
Table 11
the device and the Frequency used to read the Flash memory in Synchronous mode.
Table 11.
Wait Polarity bit (CR10)
In synchronous burst mode the Wait signal indicates whether the output data are valid or a
WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait
signal. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait
Polarity bit is set to ‘1’ the Wait signal is active High.
Data Output Configuration bit (CR9)
The Data Output Configuration bit determines whether the output remains valid for one or
two clock cycles. When the Data Output Configuration bit is ’0’ the output data is valid for
one clock cycle, when the Data Output Configuration bit is ’1’ the output data is valid for two
clock cycles.
The Data Output Configuration depends on the condition:
●
where t
and t
Configuration bit should be set to ‘1’ (two clock cycles). Refer to
data output configuration
Wait Configuration bit (CR8)
In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is
asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid.
When the Wait bit is ’0’ the Wait output pin is asserted during the wait state. When the Wait
bit is ’1’ the Wait output pin is asserted one clock cycle before the wait state.
Figure 7: X-latency and data output configuration
t
KQV
K
> t
K
shows how to set the X-Latency parameter, taking into account the speed class of
is the clock period, t
is the clock to data valid time. If this condition is not satisfied, the Data Output
30 MHz
40 MHz
54 MHz
66 MHz
86 MHz
KQV
fmax
X-latency settings
Register.
+ t
QVK_CPU
example.
QVK_CPU
t
33 ns
25 ns
19 ns
15 ns
12 ns
K
is the data setup time required by the system CPU
min
example.
Figure 7: X-latency and
X-Latency min
Configuration Register
Table 12:
2
3
4
4
5
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