TE28F800C3TA110 Micron Technology Inc, TE28F800C3TA110 Datasheet - Page 19
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TE28F800C3TA110
Manufacturer Part Number
TE28F800C3TA110
Description
Manufacturer
Micron Technology Inc
Datasheet
1.TE28F800C3TA110.pdf
(70 pages)
Specifications of TE28F800C3TA110
Density
8Mb
Access Time (max)
110ns
Interface Type
Parallel
Boot Type
Top
Address Bus
19b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
512K
Supply Current
18mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TE28F800C3TA110
Manufacturer:
TI
Quantity:
201
C3 Discrete
4.2
Figure 8:
Notes:
1.
2.
4.3
Table 5:
March 2008
290645-24
A[MAX:0]
DQ[15:0]
Symbol
CE#
OE#
RP#
A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
Unused address balls are not populated.
A
B
C
D
E
G
H
F
CE# DQ
DQ
A
A
A
A
A
A
64-Ball Easy BGA Package
Signal Descriptions
Output
22
Input/
1
Type
Input
Input
Input
Input
1
2
3
4
0
8
(2)
64-Ball Easy BGA Package
Signal Descriptions
V
OE# V
DQ
A
A
A
Top View - Ball Side
SSQ
A
2
17
6
7
5
1
0
A
WP# WE# DU A
DQ
DQ
DQ
A
DU
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
cycle.
8 Mbit: AMAX= A18
16 Mbit: AMAX = A19
32 Mbit: AMAX = A20
64 Mbit: AMAX = A21
DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read
cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense
amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption
to standby levels.
OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a
Read operation.
RESET/DEEP POWER-DOWN: Active-low input.
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to
High-Z, resets the Write State Machine, and minimizes current levels (I
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to
logic-high, the device resets all blocks to locked and defaults to the read array mode.
19
CCQ
3
18
(1)
10
9
2
DQ
RP# DU A
DQ
DQ
V
V
DU
4
CC
PP
11
3
4
DQ
DQ
V
DQ
V
DU DU
SSQ
5
CC
12
13
5
GND A
DQ
DQ
DQ
DQ
6
20
21
(1)
(1)
14
15
6
7
V
V
A
A
DU
DU
7
A
CCQ
SSQ
10
11
12
8
1,2
A
A
A
DU
DU
A
A
DU
15
14
13
16
8
9
A
B
C
D
E
F
G
H
Description
DU V
A
A
A
DU
DU
A
A
15
14
13
16
8
9
V
A
A
DU DQ
DU DQ
A
CCQ
A
SSQ
7
10
11
12
8
Bottom View - Ball Side
GND V
A
A
DU
D
D
20
21
6
15
7
(1)
(1)
14
6
DQ
V
DQ
DU RP# A
DU WE# WP# A
DU
D
SSQ
5
CC
13
12
5
DQ
DQ
DQ
V
V
DU DU
4
CC
PP
11
3
4
CCD
DQ
V
DQ
DQ
A
).
3
19
CCQ
18
(1)
10
9
2
V
OE# A
DQ
DQ
A
A
2
A
SSQ
17
6
7
5
1
0
DQ
CE#
A
A
A
A
A
22
1
1
2
3
4
0
8
(2)
Datasheet
19