CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 12

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 4-1. CYNSE70128 Signal Description (continued)
Document #: 38-02040 Rev. *F
SRAM Interface
Cascade Interface
Notes:
HIGH_SPEED
3.
4.
5.
SADR[23:0]
MULTI_HIT
Pin Name
BHO[2:0]
FULI[6:0]
DQ[71:0]
LHO[1:0]
BHI[2:0]
LHI[6:0]
ACK
EOT
ALE_L
In the previous versions of this specification, this signal was called CLK_OUT.
In previous versions of this specification, this signal was called PLL_BYPASS.
ACK and EOT require a weak external pull-down such as 47 K
WE_L
OE_L
CE_L
SSF
SSV
[5]
[5]
Type
Pin
I/O
O
O
O
T
T
T
T
T
T
T
T
T
I
I
I
I
[1]
Address/Data Bus:
mask array operations. It carries the compare data during Search operations. It also carries the SRAM
address during SRAM PIO accesses.
Read Acknowledge:
and mask array Read operations, or that the data is available on the SRAM data bus during SRAM
Read operations.
End of Transfer:
Write burst operations.
Search Successful Flag:
Search operation.
Search Successful Flag Valid:
Multiple Hit Flag:
match on this device.
High Speed:
However, in this mode, a TLSZ value of 00 is not supported when only one device is used. The valid
TLSZ values are shown in Command Register Description (Table 7-3). When the signal is LOW, the
device will run up to 83 MHz and perform 83 MSPS.
SRAM Address:
See Table 12-1 for the details of the generated SRAM address. In a database of multiple
CYNSE70128s, each corresponding bit of SADR from all cascaded devices must be connected.
SRAM Chip Enable:
CYNSE70128s, CE_L of all cascaded devices must be connected. This signal is then driven by only
one of the devices.
SRAM Write Enable:
CYNSE70128s, WE_L of all cascaded devices must be connected together. This signal is then driven
by only one of the devices.
SRAM Output Enable:
this signal (with the LRAM bit set).
Address Latch Enable:
a database of multiple CYNSE70128s, the ALE_L of all cascaded devices must be connected. This
signal is then driven by only one of the devices.
Local Hit In:
connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. All unused LHI pins are
connected to a logic 0. (For more information, see ”Depth-Cascading” on page 102.)
Local Hit Out:
connected to one input of the LHI bus of up to four downstream devices in a block of up to eight. (For
more information see ”Depth-Cascading” on page 102.)
Block Hit In:
block system, the last block can contain only seven devices because the identification code 11111 is
used for broadcast access.
Block Hit Out:
devices in the downstream blocks.
Full In:
the FULL flag for the depth-cascaded block.
Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device to generate
These pins depth-cascade the device to form a larger table. One signal of this bus is
Inputs from the previous block BHO[2:0] are tied to BHI[2:0] of the current device. In a four-
When this signal is HIGH, the device will run up to 100 MHz and perform 100 MSPS.
LHO[1] and LHO[0] are the same logical signal. Either the LHO[1] or the LHO[0] is
These outputs from the last device in a block are connected to the BHI[2:0] inputs of the
This bus contains address lines to access off-chip SRAMs that contain associative data.
This signal indicates the end of burst transfer to the data or mask array during Read or
When asserted, this signal indicates that there is more than one location having a
This signal carries the Read and Write address and data during register, data, and
This is the chip-enable control for external SRAMs. In a database of multiple
This signal indicates that valid data is available on the DQ bus during register, data,
This is the write-enable control for external SRAMs. In a database of multiple
This is the output-enable control for external SRAMs. Only the last device drives
When this signal is LOW, the addresses are valid on the SRAM address bus. In
When asserted, this signal indicates that the device is the global winner in a
Ω
When asserted, this signal qualifies the SSF signal.
or 100 K
Ω
.
Pin Description
CYNSE70128
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