CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 7

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

CYNSE70128
LIST OF TABLES
Table 4-1. CYNSE70128 Signal Description ........................................................................................ 11
Table 7-1. Register Overview ............................................................................................................... 15
Table 7-2. Search Successful Register Description .............................................................................16
Table 7-3. Command Register Description ........................................................................................... 17
Table 7-4. Information Register Description ......................................................................................... 18
Table 7-5. Read Burst Register Description ......................................................................................... 18
Table 7-6. Write Burst Register Description ......................................................................................... 19
Table 7-7. NFA Register ....................................................................................................................... 19
Table 8-1. Bit Position Match ................................................................................................................ 20
Table 10-1. Command Codes ............................................................................................................... 22
Table 10-2. Command Parameters ...................................................................................................... 22
Table 10-3. Read Command Parameters ............................................................................................. 23
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM ........................................... 23
Table 10-5. Read Address Format for Internal Registers ..................................................................... 24
Table 10-6. Read Address Format for Data and Mask Arrays .............................................................. 25
Table 10-7. Write Address Format for Data Array, Mask Array or SRAM (Single Write) ...................... 26
Table 10-8. Write Address Format for Internal Registers ..................................................................... 26
Table 10-9. Write Address Format for Data and Mask Array (Burst Write) .......................................... 27
Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 29
Table 10-11. Shift OF SSF and SSV from SADR ................................................................................. 29
Table 10-12. Hit/Miss Assumption ........................................................................................................ 30
Table 10-13. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 35
Table 10-14. Shift OF SSF and SSV from SADR ................................................................................. 35
Table 10-15. Hit/Miss Assumption ........................................................................................................ 36
Table 10-16. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 50
Table 10-17. Shift of SSF and SSV from SADR ................................................................................... 50
Table 10-18. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 52
Table 10-19. Shift OF SSF and SSV from SADR ................................................................................. 52
Table 10-20. Hit/Miss Assumption ........................................................................................................ 53
Table 10-21. Search Latency from Instruction to SRAM Access Cycle ................................................ 58
Table 10-22. Shift OF SSF and SSV from SADR ................................................................................. 58
Table 10-23. Hit/Miss Assumption ........................................................................................................ 59
Table 10-24. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 73
Table 10-25. Shift OF SSF and SSV from SADR ................................................................................. 73
Table 10-26. The Latency of Search from Cycles C and D to SRAM Access Cycle ............................ 76
Table 10-27. Shift OF SSF and SSV from SADR ................................................................................. 76
Table 10-28. Hit/Miss Assumption ........................................................................................................ 76
Table 10-29. The Latency of Search from Cycles C and D to SRAM Access Cycle ............................ 81
Table 10-30. Shift of SSF and SSV from SADR ................................................................................... 81
Table 10-31. Hit/Miss Assumption ........................................................................................................ 82
Table 10-32. The Latency of Search from Cycles C and D to SRAM Access Cycle ............................ 96
Table 10-33. Shift of SSF and SSV from SADR ................................................................................... 96
Table 10-34. Searches with CFG_L Set High ....................................................................................... 98
Table 10-35. Latency of SRAM Write Cycle from Second Cycle of Learn Instruction ........................ 101
Table 12-1. SRAM Address ................................................................................................................ 106
Table 12-2. Required Idle Cycles between Commands ...................................................................... 121
Table 15-1. Supported Operations ..................................................................................................... 124
Table 15-2. TAP Device ID Register ................................................................................................... 125
Table 16-1. DC Electrical Characteristics for CYNSE70128 .............................................................. 125
Document #: 38-02040 Rev. *F
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