CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 24

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-5 describes the Read address format for the internal registers. Figure 10-2 illustrates the timing diagram for the burst
Read of the data or mask array.
Table 10-5. Read Address Format for Internal Registers
The Read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the
RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG with the
starting address (ADR) and the length of the transfer (BLEN) before initiating the burst Read command.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the burst length (BLEN) field of RBURREG
are complete. On the last transfer, the CYNSE70128 drives the EOT signal high.
At the termination of cycle (4 + 2n), the selected device floats the ACK line to the three-state condition. The burst Read instruction
is complete, and a new operation can begin. Table 10-6 describes the Read address format for data and mask arrays for burst
Read operations.
Document #: 38-02040 Rev. *F
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM (continued)
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address supplied
• Cycle 2: The host ASIC floats DQ[71:0] to the three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in the three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives ACK and EOT from Z to LOW.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[71:0] bus, and drives the ACK
• Cycle (4 + 2n): The selected device drives the DQ[71:0] to the three-state condition, and drives the ACK and EOT signals LOW.
DQ[71:30]
Reserved
Reserved
on the DQ bus, as shown in Table 10-6. The host ASIC selects the CYNSE70128 where ID[4:0] matches the DQ[25:21] lines.
If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70128 with the LDEV bit set.
signal HIGH.
DQ[71:26]
Reserved
1: Indirect
1: Indirect
0: Direct
0: Direct
DQ[29]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
Successful
Search Register
Index (appli-
cable if DQ[29]
is indirect)
Successful
Search Register
Index (appli-
cable if DQ[29]
is indirect)
CMDV
ACK
EOT
DQ[28:26]
DQ
Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
DQ[25:21]
ID
Address
cycle
Read
A B
1
DQ[25:21] DQ[20:19] DQ[18:16]
cycle
2
ID
ID
cycle
3
cycle
11: Register
DQ[20:19]
FF
4
01: Mask
External
SRAM
Array
cycle
10:
Data0
5
cycle
6
FF
Reserved If DQ[29] is 0, this field carries the address of
Reserved If DQ[29] is 0, this field carries the address of
cycle
Data1
7
cycle
8
FF
cycle
the mask array location. If DQ[29] is 1, the
SSRI specified on DQ[28:26] is used to
generate the address of the mask array
location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.
the SRAM location. If DQ[29] is 1, the SSRI
specified on DQ[28:26] is used to generate the
address of the SRAM location: {SSR[15:2],
SSR[1] | DQ[1], SSR[0] | DQ[0]}.
DQ[18:7]
Reserved
Data2
9
cycle
10
FF
[11]
cycle
11
Data3
cycle
12
DQ[15:0]
Register Address
CYNSE70128
DQ[6:0]
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