CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 57

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The following is the sequence of operation for a single 144-bit Search command (also see “Commands and Command Param-
eters” on page 22).
The logical 144-bit search operation is shown in Figure 10-34. The entire table (eight devices of 144-bit entries) is compared to
a 144-bit word K (presented on the DQ bus in cycles A and B of the command) using the GMR and local mask bits. The GMR is
the 144-bit word specified by the even and odd global mask pair selected by the GMR Index in the command’s cycle A.
Document #: 38-02040 Rev. *F
CFG = 0101010101010101, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10],CMD[5:3]}
• Cycle B: The host ASIC continues to drive CMDV high and to apply the command code for Search command (10) on CMD[1:0].
signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with
the same bits that will be driven by this device on SADR[23:21] if it has a hit. DQ[71:0] must be driven with the 72-bit data
([143:72]) in order to be compared against all even locations. The CMD[2] signal must be driven to a logic 0.
CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus
during cycles A and B. CMD[8:6] signals must be driven with the SSR index that will be used for storing the address of the
matching entry and the hit flag (see page 8 for the description of SSR[0:7]). The DQ[71:0] is driven with 72-bit data ([71:0])
compared against all odd locations.
SADR[23:0]
CMD[10:2]
PHS_L
CMD[1:0]
|(LHI[6:0])
CMDV
LHO[1:0]
ALE_L
CLK2X
Figure 10-33. Timing Diagram for 144-bit Search Device Number 7 (Last Device)
OE_L
CE_L
WE_L
SSF
SSV
DQ
0
0
0
0
1
0
cycle
Search1
A B A B A B A B
1
A B A B A B A B
01
D1
cycle
Search2
2
01
D2
cycle
Search3
3
01
D3
cycle
4
Search4
01
D4
cycle
5
cycle
6
cycle
Search1
7
(Miss on
this device)
z
z
z
cycle
8
(Miss on
this device)
Search2
cycle
9
(Local but not
global winner)
A4
z
z
Search3
cycle
10
1
0
0
Search4
(Global
winner.)
1
1
CYNSE70128
0
0
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