P80C592FFA NXP Semiconductors, P80C592FFA Datasheet - Page 50
![](/photos/31/32/313213/sot188-2_sml.jpg)
P80C592FFA
Manufacturer Part Number
P80C592FFA
Description
Manufacturer
NXP Semiconductors
Datasheet
1.P80C592FFA.pdf
(108 pages)
Specifications of P80C592FFA
Cpu Family
80C
Device Core
80C51
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
CAN/UART
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
512Byte
# I/os (max)
40
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P80C592FFA
Manufacturer:
PANASONIC
Quantity:
1 200
Part Number:
P80C592FFA
Manufacturer:
PHI
Quantity:
20 000
Company:
Part Number:
P80C592FFA/00
Manufacturer:
SYSTECH
Quantity:
40
Part Number:
P80C592FFA/00
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
P80C592FFA/00,512
Manufacturer:
ON
Quantity:
300
Company:
Part Number:
P80C592FFA/00,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
P80C592FFA/00,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
P80C592FFA/00Ј¬512
Manufacturer:
NXP
Quantity:
702
Philips Semiconductors
13.5.15.4 Special Function Register CANSTA
CANSTA is implemented as a bit-addressable read/write register.
The bit addresses of CANSTA (7 to 0) are DFH to D8H.
Table 67 SFR CANCON in Read access (address DFH to D8H)
Table 68 Description of the CANCON bits in Read access
When reading CANSTA the Status Register of the CAN-controller is accessed.
Table 69 SFR CANCON in Write access (address DFH to D8H)
Table 70 Description of the CANSTA bits in Write access
Writing to CANSTA sets the address of the on-chip MAIN RAM (internal Data Memory) for a subsequent DMA transfer.
1996 Jun 27
BIT SYMBOL
BIT SYMBOL
to
7
6
5
4
3
2
1
0
7
0
8-bit microcontroller with on-chip CAN
RAMA7
BS
BS
ES
TS
RS
TCS
TBS
DO
RBS
RAMA7
to
RAMA0
7
7
Bus Status (see Table 37).
Error Status (see Table 37).
Transmit Status (see Table 37).
Receive Status (see Table 37).
Transmission Complete Status (see Table 37).
Transmit Buffer Access (see Table 37).
Data Overrun (see Table 37).
Receive Buffer Status (see Table 37).
RAMA6
ES
6
6
RAMA5
TS
5
5
RAMA4
RS
4
4
50
FUNCTION
FUNCTION
RAMA3
TCS
3
3
RAMA2
TBS
2
2
RAMA1
DO
1
1
Product specification
P8xC592
RAMA0
RBS
0
0