MC68150FN40 IDT, Integrated Device Technology Inc, MC68150FN40 Datasheet - Page 5

• Manufacturer Part Number: MC68150FN40
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of MC68150FN40

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: PLCC
• Pin Count: 68
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC68150
32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
X = Don’t Care (Do Not Leave Inputs Floating); = Latched Data From Processor; Z = 3-State; InX = Input (0 Signifies the MSB and 3 Signifies
TYPICAL SYSTEM CONFIGURATION
MC68150, a PAL for timing control, and various size memory devices. When a 32-bit port is required, two F245’s must be used
to buffer the PD15–PD0 bits to the D15–D0 bits of the ‘040, since the MC68150 does not support these bits. The typical system
configuration (Figure 2) illustrates communication between a 68040 and 8-, 16-, and 32-bit peripheral chips.
Table 2. 68150 TRUTH TABLE (WRITE Mode)
SIZ1
High Performance Frequency
Control Products — BR1334
LL or HH
LL or HH
LL or HH
LL or HH
LL or HH
LL or HH
LL or HH
H
H
H
H
H
H
H
H
the LSB); OutX = Output Corresponding to the Input InX
L
L
L
L
L
L
L
L
L
L
L
L
Peripheral data connections are the same as for a 68030
32-bit ports require transceivers or latched transceivers for PD15:0
68150 does not support burst mode
– Connect PD31:24 for 8-bit port
– Connect PD31:24 for upper byte 16-bit port
– Connect PD23:16 for lower byte 16-bit port
– Connect PD31:24 for upper-upper byte 32-bit port
– Connect PD23:16 for upper-middle byte 32-bit port
– Connect PD15:8 for lower-middle byte 32-bit port
– Connect PD7:0 for lower-lower byte 32-bit port
– The MC68150 only passes the upper 16 data bits on a 32-bit transfer
– One way to handle this is to connect TA of the 68150 to TBI of the 68040
A 68040 system using the MC68150 for dynamic bus sizing consists minimally of the MC68040 microprocessor, the
SIZ0
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
PA1
H
H
H
H
H
H
H
H
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
PA0
H
H
H
H
H
H
X
X
X
X
H
H
X
X
X
H
H
L
L
L
L
L
L
L
L
L
L
DSACK1
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
DSACK0
Freescale Semiconductor, Inc.
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
For More Information On This Product,
D31:24
In0
In0
In0
In0
In0
In0
In0
In0
In0
X
X
X
X
X
X
X
X
X
X
X
X
X
Go to: www.freescale.com
D23:16
Design Guidelines
In1
In1
In1
In1
In1
In1
In1
In1
In1
X
X
X
X
X
X
X
X
X
X
X
X
X
D15:8
In2
In2
In2
In2
In2
In2
In2
In2
In2
X
X
X
X
X
X
X
X
X
X
X
X
X
5
D7:0
In3
In3
In3
In3
In3
In3
In3
In3
In3
X
X
X
X
X
X
X
X
X
X
X
X
X
PD31:24
Out0
Out0
Out2
Out0
Out1
Out2
Out3
Out0
Out0
Out2
Out0
Out1
Out2
Out3
Out0
Out0
Out2
Out0
Out1
Out2
Out3
X
X
X
X
X
X
PD23:16
Out1
Out1
Out3
Out1
Out1
Out3
Out1
Out1
Out3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8-Bit WRITE to 32-Bit Peripheral
8-Bit WRITE to 16-Bit Peripheral
8-Bit WRITE to 8-Bit Peripheral
16-Bit WRITE to 32-Bit Peripheral
16-Bit WRITE to 16-Bit Peripheral
16-Bit WRITE to 8-Bit Peripheral
(2 Transfers)
16-Bit WRITE to 8-Bit Peripheral
(2 Transfers)
32-Bit WRITE to 32-Bit Peripheral
32-Bit WRITE to 16-Bit Peripheral
(2 Transfers)
32-Bit WRITE to 8-Bit Peripheral
(4 Transfers)
Description of Transfer
MC68150
MOTOROLA
Fig
NETCOM
50
52
54
56
42
44
46
48
34
36
38
40
30
32
26
28
22
24
18
16
14
5
MC68150