MC68150FN40 IDT, Integrated Device Technology Inc, MC68150FN40 Datasheet - Page 6

• Manufacturer Part Number: MC68150FN40
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of MC68150FN40

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: PLCC
• Pin Count: 68
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC68150
32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer
2. MC68040 BUS OPERATION
is High, all odd states are defined when BCLK is low. A clock edge is referenced by the state that follows the clock edge. All rising
edges are referenced by even number states. All falling edges are referenced by odd number states. DS0 is the first state of an
access. DSW represents a wait state or a mid-access transfer state. A wait state indicates an access is occurring, but that the
MC68150 is waiting on the peripheral to complete the transaction. Note that the peripheral and MPU states are distinct, though
related, to each other. The peripheral states start with S0. Figure 4 is an example transfer with the states marked.
2.1 Access Start
are held by the MC68040 throughout the access. The transfer start is asserted around only one rising edge of the clock (BCLK).
The chip select (CS) for the MC68150 is asserted while the MC68040 transfer control signals are input to the MC68150.
CS recognized (DS2). If the transfer control signals change states during this set-up time, the MC68150 operation is unpredictable.
The transfer control signals must be held valid until at least DS4. If the CS switches during the set-up time before the rising edge
of DS2, then the access may not be recognized until the next clock edge. Once asserted, CS must be held asserted until the end
of the access.
latched into the 68150 off the DS2 rising clock edge (as long as CS is recognized as described above). This latched data is internally
held by the 68150 until CS is negated at the end of a transfer.
MC68150
MOTOROLA
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An access is divided into multiple states. Each state represents half a clock period. All even states are defined when BCLK
The MC68040 begins an access by asserting the transfer control signals and transfer start (TS). The transfer control signals
The transfer control signals (A1, A0, SIZ1, SIZ0, R/W) must all be valid a set-up time before the rising edge of BCLK on which
During a write access, the data signals (D(31:0)) must be valid a set-up time before the rising edge of DS2. The ‘040 data is
Figure 4. MC68150 32-Bit to 8-Bit Transfer Example (READ or WRITE)
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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High Performance Frequency
Control Products — BR1334
NETCOM
MC68150